Vertical junction field effect transistor and method for fabricating the same

ABSTRACT

A vertical JFET  1   a  according to the present invention has an n +  type drain semiconductor portion  2 , an n-type drift semiconductor portion  3 , a p +  type gate semiconductor portion  4 , an n-type channel semiconductor portion  5 , an n +  type source semiconductor portion  7 , and a p +  type gate semiconductor portion  8 . The n-type drift semiconductor portion  3  is placed on a principal surface of the n +  type drain semiconductor portion 2 and has first to fourth regions  3   a  to  3   d  extending in a direction intersecting with the principal surface. The p +  type gate semiconductor portion  4  is placed on the first to third regions  3   a  to  3   c  of the n-type drift semiconductor portion  3 . The n-type channel semiconductor portion  5  is placed along the p +  type gate semiconductor portion  4  and is electrically connected to the fourth region  3   d  of the n-type drift semiconductor portion  3.

TECHNICAL FIELD

The present invention relates to vertical junction field effecttransistors, and methods of producing the vertical junction field effecttransistors.

BACKGROUND ART

Junction Field Effect Transistors (JFETs) are voltage-controlledsemiconductor devices configured to control an electric current betweena source electrode and a drain electrode by a gate voltage.Specifically, a JFET is a device that has a channel region between thesource electrode and the drain electrode and in contact with a gateelectrode, and that is configured to alter the thickness of a depletionlayer in a pn junction formed by a gate semiconductor layer and achannel semiconductor layer, by a voltage applied to the gate electrode,thereby controlling a drain current flowing in the channel region.

Semiconductor devices using silicon as a semiconductor material prevailnowadays. In the case of silicon-based power semiconductor devices,device types to be used differ depending upon breakdown voltages of thedevices: MOSFETs (metal/oxide/semiconductor field effect transistors)are the mainstream in low voltage systems where the device breakdownvoltage is not more than 200 V; IGBTs (insulated gate bipolartransistors), thyristors, or the like are the mainstream in high voltagesystems where the device breakdown voltage is higher than 200 V.

As for the JFETs, static induction transistors (SITs), a type of JFETs,have been developed and manufactured as power semiconductors. The SITshave the device structure similar to the JFETs; precisely, the staticcharacteristics of the JFETs are the pentode characteristics withsaturation, whereas the static characteristics of the SITs are thetriode characteristics characterized by unsaturation.

DISCLOSURE OF THE INVENTION

In recent years, wide-gap semiconductor materials such as siliconcarbide (SiC) and gallium nitride (GaN) are drawing attention assemiconductor materials capable of implementing excellent powersemiconductor devices capable of high-frequency operation with higherbreakdown voltage, lower loss, and higher output than silicon.Particularly, as to the higher breakdown voltage and lower loss, theloss two or more digits lower than that by silicon can be expected atthe breakdown voltage of 1 kV. Among the currently existing MOSstructure devices, however, no device has been implemented with expectedlow loss because the surface mobility is low immediately below the oxidefilm.

As a power device type, the MOS structure has the advantage of voltagedrive and normally-off type. Inventors then focused attention on theJFETs with characteristics characterized by mobility inside crystals,which have not been developed very much with silicon, and studiedhigh-breakdown-voltage low-loss devices. In addition, it is feasible toimplement a JFET of the normally-off type device. Inventors judged thatthe structure of letting the electric current flow in the direction fromthe front surface to the back surface of the substrate was the preferredstructure for power devices, and studied vertical JFETs.

An object of the present invention is therefore to provide verticaljunction field effect transistors capable of achieving low loss whilemaintaining high drain blocking voltage, and to provide methods ofproducing the vertical junction field effect transistors.

First, Inventors have conducted studies for realizing low loss in thevertical JFET structure and accomplished the invention as describedbelow.

A vertical junction field effect transistor according to the presentinvention comprises a drain semiconductor portion, a drift semiconductorportion, a buried semiconductor portion, a channel semiconductorportion, a source semiconductor portion, and a gate semiconductorportion. The drift semiconductor portion is placed on a principalsurface of the drain semiconductor portion and has first, second, third,and fourth regions extending in a predetermined axial directionintersecting with the principal surface. The buried semiconductorportion has a conductivity type opposite to a conductivity type of thedrift semiconductor portion and is placed on the first, second, andthird regions of the drift semiconductor portion. The channelsemiconductor portion is placed along the buried semiconductor portion,has the conductivity type opposite to the conductivity type of theburied semiconductor portion, and is electrically connected to thefourth region of the drift semiconductor portion. The sourcesemiconductor portion is placed on the channel semiconductor portion andthe first region of the drift semiconductor portion. The gatesemiconductor portion has a conductivity type opposite to a conductivitytype of the drain semiconductor portion and is placed on the channelsemiconductor portion and the third and fourth regions. The gatesemiconductor portion has a plurality of projections extending in adirection from the third region toward the fourth region, the channelsemiconductor portion is placed between the projections, and theprojections are connected to the buried semiconductor portion.

In the vertical junction field effect transistor of this configuration,the buried semiconductor portion and the channel semiconductor portioncan be arranged on the drift semiconductor portion. In this structure,the fundamental loss of the device is the sum of loss of the channelsemiconductor portion and loss of the drift semiconductor portion. Forthis reason, if the breakdown voltage of the device were raised to ahigh voltage by the channel semiconductor portion only, the impurityconcentration of the channel would be low and the channel length wouldbe long, so as to increase the loss of the device. Therefore, thefollowing advantages can be enjoyed by providing the channelsemiconductor portion in charge of control of the drain current and thedrift semiconductor portion in charge of the breakdown voltage of thedevice, as in the structure of the present invention. Firstly, thechannel semiconductor portion permits increase of the impurityconcentration and decrease of the channel length, so as to decrease theloss of the channel semiconductor portion. Secondly, the driftsemiconductor portion can attain a desired drain blocking voltage by itsimpurity concentration and thickness, so that the loss can be minimized.Thirdly, the device loss in the limited area is reduced by the verticalstack of the drift semiconductor portion and the channel semiconductorportion.

Another vertical junction field effect transistor comprises a drainsemiconductor portion, a drift semiconductor portion, a buriedsemiconductor portion, a channel semiconductor portion, a sourcesemiconductor portion, and a plurality of gate semiconductor portions.The drift semiconductor portion is placed on a principal surface of thedrain semiconductor portion and has first, second, third, and fourthregions extending in a predetermined axial direction intersecting withthe principal surface. The buried semiconductor portion has aconductivity type opposite to a conductivity type of the driftsemiconductor portion and is placed on the first, second, and thirdregions of the drift semiconductor portion. The channel semiconductorportion is placed along the buried semiconductor portion, has theconductivity type opposite to the conductivity type of the buriedsemiconductor portion, and is electrically connected to the fourthregion of the drift semiconductor portion. The source semiconductorportion is placed on the channel semiconductor portion and the firstregion of the drift semiconductor portion. The plurality of gatesemiconductor portions have a conductivity type opposite to aconductivity type of the drain semiconductor portion and are placed onthe channel semiconductor portion and the third and fourth regions. Eachof the plurality of gate semiconductor portions extends in a directionfrom the third region toward the fourth region, the channelsemiconductor portion is placed between the gate semiconductor portions,and each gate semiconductor portion is connected to the buriedsemiconductor portion.

Since the transistor of this configuration has the channel semiconductorportion between the plurality of gate semiconductor portions, thechannel semiconductor portion is controlled from both sides. Therefore,the thickness of the channel can be increased and the loss can bereduced.

Another vertical junction field effect transistor comprises a drainsemiconductor portion, a drift semiconductor portion, a buriedsemiconductor portion, a channel semiconductor portion, and a gatesemiconductor portion. The drift semiconductor portion is placed on aprincipal surface of the drain semiconductor portion and has first,second, third, and fourth regions extending in a predetermined axialdirection intersecting with the principal surface. The buriedsemiconductor portion is placed on a principal surface of the driftsemiconductor portion and is placed on the first, second, and thirdregions extending in a predetermined axial direction intersecting withthe principal surface. The channel semiconductor portion is placed alongthe buried semiconductor portion, has a conductivity type opposite to aconductivity type of the buried semiconductor portion, and iselectrically connected to the fourth region of the drift semiconductorportion. The gate semiconductor portion has a conductivity type oppositeto a conductivity type of the drift semiconductor portion and is placedon the channel semiconductor portion and the third and fourth regions.The gate semiconductor portion has a plurality of projections extendingin a direction from the third region toward the fourth region, thechannel semiconductor portion is placed between the projections, and thedrift semiconductor portion is connected to the buried semiconductorportion. The drift semiconductor portion has a fifth region extending inthe axial direction intersecting with the principal surface of the drainsemiconductor portion, and the transistor further comprises a secondsemiconductor portion having a conductivity type opposite to aconductivity type of the drain semiconductor portion and placed abovethe fifth region. The second semiconductor portion extends from theburied semiconductor portion in the predetermined axial direction alonga source semiconductor portion.

Since the transistor of this configuration has the channel semiconductorportion between the buried semiconductor portion and the gatesemiconductor portion, the channel semiconductor portion is controlledfrom both sides. Therefore, the thickness of the channel can beincreased and the loss can be reduced.

Any one of the foregoing vertical junction field effect transistorsfurther comprises a first semiconductor portion. The first semiconductorportion is placed on the channel semiconductor portion and the first andsecond regions of the drift semiconductor portion and has the sameconductivity type as the source semiconductor portion. A dopantconcentration of the first semiconductor portion is preferably lowerthan a dopant concentration of the channel semiconductor portion.

In the transistor of this configuration, the first semiconductor portionis placed between the channel semiconductor portion and the sourcesemiconductor portion. This structure can absorb tolerances of thicknessof the channel semiconductor portion associated with etching. Therefore,individual differences can be reduced in electrical characteristicsamong vertical junction field effect transistors.

Another vertical junction field effect transistor comprises a drainsemiconductor portion, a drift semiconductor portion, a buriedsemiconductor portion, a plurality of gate semiconductor portions, achannel semiconductor portion, a connection semiconductor portion, afirst aggregate semiconductor portion, a second aggregate semiconductorportion, and a source semiconductor portion. The drift semiconductorportion is placed on a principal surface of the drain semiconductorportion and has first to fifth regions extending in a predeterminedaxial direction intersecting with a reference plane extending along theprincipal surface. The buried semiconductor portion has a conductivitytype opposite to a conductivity type of the drift semiconductor portionand is placed along the reference plane on the first to fourth regionsof the drift semiconductor portion. The plurality of gate semiconductorportions are placed along the reference plane on the second to fourthregions of the drift semiconductor portion and have the sameconductivity type as the conductivity type of the buried semiconductorportion. The channel semiconductor portion is placed between the buriedsemiconductor portion and the plurality of gate semiconductor portions,and between the plurality of gate semiconductor portions, and has theconductivity type opposite to the conductivity type of the buriedsemiconductor portion. The connection semiconductor portion has the sameconductivity type as the conductivity type of the buried semiconductorportion and the channel semiconductor portion, extends in thepredetermined axial direction, and connects the buried semiconductorportion and the plurality of gate semiconductor portions. The firstaggregate semiconductor portion connects the channel semiconductorportion on the first region of the drift semiconductor portion. Thesecond aggregate semiconductor portion connects the channelsemiconductor portion on the fifth region of the drift semiconductorportion. The source semiconductor portion is placed above the firstregion of the drift semiconductor portion and is connected to the firstaggregate semiconductor portion.

In the vertical junction field effect transistor of this configuration,the channel region is placed between the buried semiconductor portionand the plurality of gate semiconductor portions. Accordingly, it isfeasible to increase the channel region that can be controlled by thegate semiconductor portions. In addition, the buried semiconductorportion and the channel semiconductor portion can be arranged on thedrift semiconductor portion. Therefore, a desired drain blocking voltagecan be attained by the thickness of the drift semiconductor portion.

A further vertical junction field effect transistor comprises a drainsemiconductor portion, a drift semiconductor portion, a buriedsemiconductor portion, a plurality of gate semiconductor portions, achannel semiconductor portion, a connection semiconductor portion, afirst aggregate semiconductor portion, a second aggregate semiconductorportion, a source semiconductor portion, and a third connectionsemiconductor portion. The drift semiconductor portion is placed on aprincipal surface of the drain semiconductor portion and has first tofifth regions extending in a predetermined axial direction intersectingwith a reference plane extending along the principal surface. The buriedsemiconductor portion has a conductivity type opposite to a conductivitytype of the drift semiconductor portion and is placed along thereference plane on the first to fourth regions of the driftsemiconductor portion. The plurality of gate semiconductor portions areplaced along the reference plane on the second to fourth regions of thedrift semiconductor portion and have the same conductivity type as theconductivity type of the buried semiconductor portion. The channelsemiconductor portion is placed between the buried semiconductor portionand the plurality of gate semiconductor portions, and between theplurality of gate semiconductor portions, and has the conductivity typeopposite to the conductivity type of the buried semiconductor portion.The connection semiconductor portion has the same conductivity type asthe conductivity type of the channel semiconductor portion and connectsthe plurality of gate semiconductor portions. The first aggregatesemiconductor portion connects the channel semiconductor portion on thefirst region of the drift semiconductor portion. The second aggregatesemiconductor portion connects the channel semiconductor portion on thefifth region of the drift semiconductor portion. The sourcesemiconductor portion is placed above the first region of the driftsemiconductor portion and is connected to the first aggregatesemiconductor portion. The drift semiconductor portion has a sixthregion provided on a principal surface thereof and extending in thedirection intersecting with the principal surface. The third connectionsemiconductor portion has a conductivity type opposite to a conductivitytype of the drain semiconductor portion and is placed above the sixthregion. The third connection semiconductor portion is placed along thefirst aggregate semiconductor portion.

In this configuration, the plurality of gate semiconductor portions areelectrically connected through the third connection semiconductorportion to the buried semiconductor portion. This permits the buriedsemiconductor portion and the plurality of gate semiconductor portionsboth to be used as a gate. Therefore, it increases the thickness of thechannel that can be controlled.

In the vertical junction field effect transistors, preferably, athickness of the gate semiconductor portion and the channelsemiconductor portion is smaller than a space between the sourcesemiconductor portion and the buried semiconductor portion on the firstregion of the drift semiconductor portion.

In the vertical junction field effect transistors, preferably, athickness of the gate semiconductor portions and the channelsemiconductor portion on the second to fourth regions of the driftsemiconductor portion is smaller than a space between the sourcesemiconductor portion and the buried semiconductor portion on the firstregion of the drift semiconductor portion.

In these transistors, the buried semiconductor portion can be separatedfrom the source semiconductor portion. This improves the breakdownvoltage between the gate and the source. Since the distance between thechannel semiconductor portion and the source semiconductor portion istaken in the vertical direction, the chip size of the transistor willnot increase even if the distance is large.

In the vertical junction field effect transistors, preferably, a spacebetween the projections of the gate semiconductor portion is determinedso that the vertical junction field effect transistor can exhibit thenormally-off characteristic.

In the vertical junction field effect transistor, preferably, a spacebetween the projections of the gate semiconductor portion and a spacebetween the projections of the gate semiconductor portion and the buriedsemiconductor portion are determined so that the vertical junction fieldeffect transistor can exhibit the normally-off characteristic.

In the vertical junction field effect transistors, preferably, a spacebetween the gate semiconductor portions, and a space between the gatesemiconductor portions and the buried semiconductor portion aredetermined so that the vertical junction field effect transistor canexhibit the normally-off characteristic.

In these vertical junction field effect transistors, the thickness ofthe channel semiconductor portion can be determined by etching. For thisreason, it becomes easy to decrease the impurity concentration andthickness of the channel semiconductor portion so that the depletionlayer caused by a diffusion potential between each gate semiconductorportion or the buried semiconductor portion and the channelsemiconductor portion having the conductivity type opposite to that ofthe semiconductor portion spreads over the entire area of the channelsemiconductor portion. Therefore, it becomes feasible to deplete thechannel semiconductor portion, even without application of a gatevoltage, and to substantialize the transistor of the normally-off type.

In the vertical junction field effect transistor, the channelsemiconductor portion has a structure in which low-concentration layersand high-concentration layers are alternately stacked. The thickness ofeach layer is of nm (nanometer: 10⁻⁹ m) order. In this structure, thequantum effect causes carriers to migrate from the high-concentrationlayers with majority carriers therein into the low-concentration layerswith larger carrier mobility. This results in increasing the electriccurrent flowing in the channel semiconductor portion and reducing theloss of the channel semiconductor portion.

The drift semiconductor portion of the vertical junction field effecttransistor preferably has: an electroconductive semiconductor regionextending along a reference plane intersecting with the principalsurface of the drain semiconductor portion, having the same conductivitytype as the conductivity type of the drain semiconductor portion, andelectrically connected to the channel semiconductor portion; and anon-electroconductive semiconductor region placed next to theelectroconductive semiconductor region, having the conductivity typeopposite to the conductivity type of the drain semiconductor portion,and electrically connected to the buried semiconductor portion. Theelectroconductive semiconductor region and the non-electroconductivesemiconductor region are preferably formed in the same direction as adirection in which the first to fourth regions of the driftsemiconductor portion are arranged, or in a direction intersectingtherewith.

In the vertical junction field effect transistor of this configuration,the loss of the drift semiconductor portion can be reduced. Namely, whena voltage is applied so as to let the drain current flow in the gatesemiconductor portion, the drain current controlled in the channelsemiconductor portion flows via the electroconductive semiconductorregion of the drift semiconductor portion to the drain semiconductorportion. On the other hand, when a voltage is applied so as not to letthe drain current flow in the gate semiconductor portion, a stateequivalent to a kind of dielectric is established because the impurityconcentration and the thickness of each semiconductor region aredetermined so as to deplete both the electroconductive semiconductorregion and the non-electroconductive semiconductor region of the driftsemiconductor portion. In such a state the drift semiconductor portionhas a constant electric field intensity, and thus the thickness of thedrift semiconductor portion can be half of that in the case where thedrift semiconductor portion is not provided with the electroconductivesemiconductor region and the non-electroconductive semiconductor region.Therefore, for achieving a desired drain blocking voltage, the impurityconcentration of the electroconductive semiconductor region can beincreased and the thickness of the drift semiconductor portion can bedecreased to half. This results in decreasing the loss of the driftsemiconductor portion.

In the vertical junction field effect transistors as described above,each of the semiconductor portions such as the drain semiconductorportion, the drift semiconductor portion, the buried semiconductorportion, the gate semiconductor portion, the channel semiconductorportion, the connection semiconductor portion, and the sourcesemiconductor portion is preferably made of SiC, GaN, or the like whichis a wide-gap semiconductor material. A wide-gap semiconductor hasexcellent characteristics as a power device semiconductor material, suchas a larger bandgap and greater maximum breakdown field than silicon.Accordingly, lower loss can be realized, particularly, in comparisonwith silicon.

A production method of a vertical junction field effect transistorcomprises a step of forming a first semiconductor layer of a firstconductivity type on a substrate of the first conductivity type, whereina principal surface of the first semiconductor layer has first to fourthregions arranged in order in a predetermined axial direction; a step ofintroducing a dopant of a second conductivity type into the first tothird regions of the principal surface of the first semiconductor layerto form a buried semiconductor portion; a step of forming a secondsemiconductor layer of the first conductivity type on the firstsemiconductor layer; a step of forming a source semiconductor layer ofthe first conductivity type on the second semiconductor layer; a step ofetching the source semiconductor layer above at least one of the second,third, and fourth regions of the principal surface of the firstsemiconductor layer, up to the first semiconductor layer to expose apredetermined region of the second semiconductor layer, wherein thepredetermined region has a plurality of first portions extending in thepredetermined axial direction, and a second portion defined so as toembrace the plurality of portions; and a step of introducing a dopant ofthe second conductivity type for a gate semiconductor portion into theplurality of first portions to form a first semiconductor portion of thesecond conductivity type.

Preferably, the production method of the vertical junction field effecttransistor further comprises a step of introducing a dopant of thesecond conductivity type for the gate semiconductor portion into thesecond portion to form a second semiconductor portion of the secondconductivity type, and a depth of the second semiconductor portion issmaller than a depth of the first semiconductor portion.

In the production method of the vertical junction field effecttransistor, preferably, the first semiconductor portion is formed so asto be connected to the buried semiconductor portion.

Another production method of a vertical junction field effect transistorcomprises a first semiconductor layer forming step of forming a firstsemiconductor layer of a first conductivity type on a substrate of thefirst conductivity type, wherein a principal surface of the firstsemiconductor layer has first to fourth regions arranged in order in apredetermined axial direction; a buried semiconductor portion formingstep of introducing a dopant of a second conductivity type into thefirst to third regions of the principal surface of the firstsemiconductor layer to form a buried semiconductor portion; a secondsemiconductor layer forming step of forming a second semiconductor layerof the first conductivity type on the first semiconductor layer; asecond semiconductor region step of introducing a dopant of the secondconductivity type for a gate semiconductor portion into the secondsemiconductor layer on the second and third regions of the principalsurface of the first semiconductor layer up to a predetermined depth toform a second semiconductor region of the second conductivity type; achannel semiconductor portion forming step of repeating the secondsemiconductor layer forming step and the second semiconductor regionstep before obtaining a desired number of said second semiconductorlayers, to form a stack of gate semiconductor portions and channelsemiconductor portions; and a source semiconductor portion forming stepof forming a source semiconductor portion on the channel semiconductorportion.

In the production method of the vertical junction field effecttransistor, preferably, the second semiconductor layer forming stepcomprises forming the second semiconductor layer of the firstconductivity type in a predetermined thickness on the firstsemiconductor layer, and the channel semiconductor portion forming stepcomprises introducing the dopant of the second conductivity type so asto achieve a maximum concentration in a predetermined depth in thesecond semiconductor layer, thereby forming the stack of gatesemiconductor portions and channel semiconductor portions.

In the production method of the vertical junction field effecttransistor, preferably, the channel semiconductor portion forming stepcomprises alternately introducing a first dopant and a second dopant soas to achieve a maximum concentration in a predetermined depth in thesecond semiconductor layer, thereby forming the stack of gatesemiconductor portions and channel semiconductor portions.

In the production method of the vertical junction field effecttransistor, preferably, the channel semiconductor portion forming stepcomprises a connection region forming step of forming a secondsemiconductor connection region of the second conductivity type so as toconnect interiors of the second semiconductor layers to each other.

In the production method of the vertical junction field effecttransistor, preferably, the step of forming the first semiconductorlayer comprises forming the first semiconductor layer so as to form anelectroconductive semiconductor layer of the same conductivity type asthe substrate of the first conductivity type, form anon-electroconductive semiconductor layer of the conductivity typeopposite to that of the electroconductive semiconductor layer, on theelectroconductive semiconductor layer, and electrically connect theelectroconductive semiconductor layer to the channel semiconductorportion.

In the production method of the vertical junction field effecttransistor, preferably, the step of forming the first semiconductorlayer comprises forming the first semiconductor layer so as to form anon-electroconductive semiconductor layer of the conductivity typeopposite to the substrate of the first conductivity type, form anelectroconductive semiconductor layer of the conductivity type oppositeto that of the non-electroconductive semiconductor layer, on thenon-electroconductive semiconductor layer, and electrically connect theelectroconductive semiconductor layer to the channel semiconductorportion.

In the production method of the vertical junction field effecttransistor, preferably, the step of forming the first semiconductorlayer comprises forming the electroconductive semiconductor layer andthe non-electroconductive semiconductor layer in a directionintersecting with the principal surface of the substrate, therebyforming the first semiconductor layer.

Preferably, the vertical junction field effect transistor furthercomprises a source electrode electrically connected to the sourcesemiconductor portion and the second semiconductor portion, and theburied semiconductor portion is electrically connected through thesecond semiconductor portion to the source electrode.

In the vertical junction field effect transistor of this type, theburied semiconductor portion and the source semiconductor portion areelectrically connected to the same source electrode by connecting thesecond semiconductor portion to the source electrode. This turns thegate-drain capacitance component into the gate-source capacitancecomponent, enabling high-frequency operation.

A vertical junction field effect transistor according to the presentinvention comprises a drain semiconductor portion, a drift semiconductorportion, a buried semiconductor portion, a channel semiconductorportion, a source semiconductor portion, a first gate semiconductorportion, a first gate electrode, and a source electrode. The driftsemiconductor portion is placed on a principal surface of the drainsemiconductor portion and has first, second, third, and fourth regionsextending in a direction intersecting with the principal surface. Theburied semiconductor portion has a conductivity type opposite to aconductivity type of the drift semiconductor portion and is placed onthe first, second, and fourth regions of the drift semiconductorportion. The channel semiconductor portion is placed along the buriedsemiconductor portion on the first and second regions, has aconductivity type different from the conductivity type of the buriedsemiconductor portion, and is electrically connected to the third regionof the drift semiconductor portion. The source semiconductor portion isplaced on the channel semiconductor portion and the first region of thedrift semiconductor portion. The first gate semiconductor portion hasthe same conductivity type as the buried semiconductor portion, iselectrically connected to the buried semiconductor portion, and isplaced above the fourth region of the drift semiconductor portion. Thefirst gate electrode is electrically connected to the first gatesemiconductor portion above the fourth region of the drift semiconductorportion. The source electrode is electrically connected to the sourcesemiconductor portion above the first region of the drift semiconductorportion, is electrically insulated from the first gate electrode abovethe first gate electrode, and is placed above the first, second, third,and fourth regions of the drift semiconductor portion.

In the vertical junction field effect transistor of this configuration,the buried semiconductor portion and the channel semiconductor portion,and the first gate electrode and source electrode can be arranged on thedrift semiconductor portion. In this structure, the fundamental loss ofthe device is the sum of the loss of the channel semiconductor portionand the loss of the drift semiconductor portion. For this reason, if thebreakdown voltage of the device were increased to a high voltage by thechannel semiconductor portion only, the impurity concentration of thechannel would be reduced and the channel length would be increased, soas to increase the loss of the device. Therefore, the followingadvantages can be enjoyed by providing the channel semiconductor portionin charge of control of the drain current and the drift semiconductorportion in charge of the breakdown voltage of the device, as in thestructure of the present invention. Firstly, the channel semiconductorportion permits increase of the impurity concentration and decrease ofthe channel length, so as to decrease the loss of the channelsemiconductor portion. Secondly, the drift semiconductor portion canattain a desired drain blocking voltage by its impurity concentrationand thickness, so that the loss can be minimized. Thirdly, the deviceloss in the limited area is reduced by the vertical stack of the driftsemiconductor portion and the channel semiconductor portion.

Preferably, the vertical junction field effect transistor furthercomprises a second gate semiconductor portion. The second gatesemiconductor portion has a conductivity type opposite to a conductivitytype of the drain semiconductor portion and is placed above the secondregion or above the second and third regions of the drift semiconductorportion. The channel semiconductor portion is placed between the firstgate semiconductor portion and the second gate semiconductor portion. Asecond gate electrode electrically connected to the second gatesemiconductor portion and electrically isolated under the sourceelectrode is placed above the second region or above the second andthird regions of the drift semiconductor portion.

Since the transistor of this configuration has the channel semiconductorportion between the first gate buried semiconductor portion and thesecond gate semiconductor portion, the channel semiconductor portion iscontrolled from both sides. Therefore, the thickness of the channel canbe increased and the loss can be reduced.

In the vertical junction field effect transistor, the first gatesemiconductor portion and the source semiconductor portion areelectrically connected by the source electrode, whereby only the secondgate semiconductor portion serves as a gate electrode. Feedbackcapacitance (gate-drain capacitance)÷mutual conductance is often used asan index indicating the operating frequency of the transistor. Since theconnection of the first gate semiconductor portion to the sourceelectrode eliminates the capacitance component due to the drainsemiconductor portion and the buried semiconductor portion from thefeedback capacitance, the transistor can operate in a higher frequencyregion.

The vertical junction field effect transistor comprises connectionsemiconductor portions. The connection semiconductor portions have thesame conductivity type as the buried semiconductor portion, penetratethe channel semiconductor portion so as to electrically connect thesecond gate semiconductor portion and the buried semiconductor portion,and are scattered above the second region of the drift semiconductorportion. This structure obviates the need for the fourth region of thedrift semiconductor portion and the first gate semiconductor portion,whereby the device area can be reduced with the same loss.

The vertical junction field effect transistor further comprises a firstsemiconductor portion. The first semiconductor portion is placed on thechannel semiconductor portion and the first region of the driftsemiconductor portion and has the same conductivity type as aconductivity type of the source semiconductor portion. An impurityconcentration of the first semiconductor portion is preferably lowerthan an impurity concentration of the channel semiconductor portion.

In the transistor of this configuration, the first semiconductor portionis placed between the channel semiconductor portion and the sourcesemiconductor portion. This structure can absorb tolerances of thicknessof the channel semiconductor portion associated with etching. Therefore,individual differences can be reduced in electrical characteristicsamong vertical junction field effect transistors.

In the vertical junction field effect transistor, at least one of thefirst and second gate electrodes is provided as a gate electrode in aperipheral portion of a primitive cell (block) or chip comprised of aplurality of transistors. In the transistor of this configuration, thefirst gate semiconductor portion and the source semiconductor portionare preferably electrically connected by the source electrode. Thevertical junction field effect transistor of this type permitssimultaneous formation of the gate electrode and the source electrode,so that the production steps can be simplified.

The vertical junction field effect transistor may be configured so thata heterojunction semiconductor material is provided as a second gateelectrode to comprise a heterojunction of the second gate semiconductorportion and the channel semiconductor portion. The transistor of thisstructure obviates the need for the step of forming the second gatesemiconductor portion, thus simplifying the production steps.

In the vertical junction field effect transistor, preferably, athickness of the channel semiconductor portion placed above the secondregion of the drift semiconductor portion is smaller than a spacebetween the source semiconductor portion and the buried semiconductorportion placed on the first region of the drift semiconductor portion.In the transistor of this configuration, the buried semiconductorportion and the second gate semiconductor portion can be separated fromthe source semiconductor portion. This improves the breakdown voltagebetween the gate and the source. Since the distance between the channelsemiconductor portion and the source semiconductor portion is taken inthe vertical direction, the chip size of the transistor will notincrease even if this distance is large.

In the vertical junction field effect transistor, preferably, thethickness of the channel semiconductor portion on the buriedsemiconductor portion, or the thickness of the channel semiconductorportion of the same conductivity type as the conductivity type of thedrain semiconductor portion, which is located between the buriedsemiconductor portion and the second gate semiconductor portion, isdetermined so that the vertical junction field effect transistor canexhibit the normally-off characteristic.

In the vertical junction field effect transistor of this configuration,the thickness of the channel semiconductor portion can be determined byetching. For this reason, it becomes easy to decrease the impurityconcentration and thickness of the channel semiconductor portion so thatthe depletion layer caused by a built-in potential between each gatesemiconductor portion or the buried semiconductor portion and thechannel semiconductor portion having the conductivity type opposite tothat of the semiconductor portion spreads over the entire area of thechannel semiconductor portion. Therefore, it becomes feasible to depletethe channel semiconductor portion, even without application of a gatevoltage, and to substantialize the transistor of the normally-off type.

In the vertical junction field effect transistor, the channelsemiconductor portion has a structure in which low-concentration layersand high-concentration layers are alternately stacked. The thickness ofeach layer is of nm (nanometer: 10⁻⁹ m) order. In this structure, thequantum effect causes carriers to migrate from the high-concentrationlayers with majority carriers therein into the low-concentration layerswith larger carrier mobility. This results in increasing the electriccurrent flowing in the channel semiconductor portion and reducing theloss of the channel semiconductor portion.

Preferably, the drift semiconductor portion of the vertical junctionfield effect transistor has an electroconductive semiconductor regionextending along a reference plane intersecting with the principalsurface of the drain semiconductor portion, having the same conductivitytype as the drain semiconductor portion, and electrically connected fromthe third region of the drift semiconductor portion to the channelsemiconductor portion; and a non-electroconductive semiconductor regionplaced next to the electroconductive semiconductor region, having theconductivity type opposite to the conductivity type of the drainsemiconductor portion, and electrically connected to the buriedsemiconductor portion. Preferably, the electroconductive semiconductorregion and the non-electroconductive semiconductor region are formed inthe same direction as a direction in which the first to fourth regionsof the drift semiconductor portion are arranged, or in a directionintersecting therewith.

In the vertical junction field effect transistor of this configuration,the loss of the drift semiconductor portion can be reduced. Namely, whena voltage is applied so as to let the drain current flow in the gatesemiconductor portion, the drain current controlled in the channelsemiconductor portion flows via the electroconductive semiconductorregion of the drift semiconductor portion to the drain semiconductorportion. On the other hand, when a voltage is applied so as not to letthe drain current flow in the gate semiconductor portion, a stateequivalent to a kind of dielectric is established because the impurityconcentration and the thickness of each semiconductor region aredetermined so as to deplete both the electroconductive semiconductorregion and the non-electroconductive semiconductor region of the driftsemiconductor portion. In such a state the drift semiconductor portionhas a constant electric field intensity, and thus the thickness of thedrift semiconductor portion can be half of that in the case where thedrift semiconductor portion is not provided with the electroconductivesemiconductor region and the non-electroconductive semiconductor region.Therefore, for achieving a desired drain breakdown voltage, the impurityconcentration of the electroconductive semiconductor region can beincreased and the thickness of the drift semiconductor portion can bedecreased to half. This results in decreasing the loss of the driftsemiconductor portion.

In the vertical junction field effect transistor of this type, each ofthe semiconductor portions such as the drain semiconductor portion, thedrift semiconductor portion, the first gate semiconductor portion, andthe channel semiconductor portion is preferably made of SiC, GaN, or thelike which is a wide-gap semiconductor material. A wide gapsemiconductor has excellent characteristics as a power devicesemiconductor material, such as a larger bandgap and greater maximumbreakdown field than silicon. Accordingly, lower loss can be realized,particularly, in comparison with silicon.

A production method of a vertical junction field effect transistorcomprises a step of forming a drift semiconductor layer having first,second, third, and fourth regions, on a substrate of a firstconductivity type; a step of introducing an impurity of a conductivitytype opposite to a conductivity type of the drift semiconductor layer,into the first, second, and fourth regions of the drift semiconductorlayer to form a buried semiconductor portion; a step of forming achannel semiconductor portion having a conductivity type different fromthe conductivity type of the buried semiconductor portion, on the buriedsemiconductor portion and the drift semiconductor layer; a step offorming a source semiconductor portion above the first region of thedrift semiconductor layer; a step of introducing an impurity of the sameconductivity type as the conductivity type of the buried semiconductorportion, into a portion above the fourth region of the driftsemiconductor layer to form a first gate semiconductor portion; a stepof forming a first gate electrode electrically connected to the firstgate semiconductor portion; a step of forming an interlayer filmelectrically isolated from the first gate electrode; and a step offorming a source electrode electrically connected to the sourcesemiconductor portion, on the interlayer film.

Preferably, the production method of the vertical junction field effecttransistor further comprises a step of introducing an impurity of thesame conductivity type as the conductivity type of the first gatesemiconductor portion, into the second region or into the second andthird regions of the drift semiconductor layer, prior to the step offorming the first gate semiconductor portion, to form a second gatesemiconductor portion, and a second gate electrode electricallyconnected to the second gate semiconductor portion is formed in the stepof forming the first gate electrode.

Another production method of a vertical junction field effect transistorpreferably comprises a step of forming a drift semiconductor layerhaving first, second, third, and fourth regions, on a substrate of afirst conductivity type; a step of introducing an impurity of aconductivity type opposite to a conductivity type of the driftsemiconductor layer, into the first, second, and fourth regions of thedrift semiconductor layer to form a buried semiconductor portion; a stepof forming a channel semiconductor portion having a conductivity typedifferent from the conductivity type of the buried semiconductorportion, on the buried semiconductor portion and the drift semiconductorlayer; a step of forming a source semiconductor portion above the firstregion of the drift semiconductor layer; a step of introducing animpurity of the same conductivity type as the conductivity type of theburied semiconductor portion, into the second region or into the secondand third regions of the drift semiconductor layer to form a second gatesemiconductor portion; a step of introducing an impurity of the sameconductivity type as the conductivity type of the buried semiconductorportion, into a portion above the fourth region of the driftsemiconductor layer to form a first gate semiconductor portion; a stepof forming a second gate electrode electrically connected to the secondgate semiconductor portion; and a step of forming a source electrode forsimultaneously electrically connecting the first gate semiconductorportion and the source semiconductor portion.

Another production method of a vertical junction field effect transistorpreferably comprises a step of forming a drift semiconductor layerhaving first, second, third, and fourth regions, on a substrate of afirst conductivity type; a step of introducing an impurity of aconductivity type opposite to a conductivity type of the driftsemiconductor layer, into the first, second, and fourth regions of thedrift semiconductor layer to form a buried semiconductor portion; a stepof forming a channel semiconductor portion having a conductivity typedifferent from the conductivity type of the buried semiconductorportion, on the buried semiconductor portion and the drift semiconductorlayer; a step of forming a source semiconductor portion above the firstregion of the drift semiconductor layer; a step of introducing animpurity having the same conductivity type as the conductivity type ofthe buried semiconductor portion, into the second region or into thesecond and third regions of the drift semiconductor layer to form asecond gate semiconductor portion; a step of introducing an impurity ofthe same conductivity type as the conductivity type of the buriedsemiconductor portion, into a portion above the second region of thedrift semiconductor layer to form a connection semiconductor portionconnecting the second gate semiconductor portion and the buriedsemiconductor portion; and a step of forming a second gate electrodeelectrically connected to the second gate semiconductor portion.

Preferably, the production method of the vertical junction field effecttransistor further comprises a step of forming a first semiconductorportion having the same conductivity type as the source semiconductorportion, on the channel semiconductor portion, prior to the step offorming the source semiconductor portion, and an impurity concentrationof the first semiconductor portion is lower than an impurityconcentration of the channel semiconductor portion.

In the production method of the vertical junction field effecttransistor, preferably, the step of forming the drift semiconductorlayer comprises forming the drift semiconductor layer so as to form anelectroconductive semiconductor layer of the same conductivity type asthe drain semiconductor portion, form a non-electroconductivesemiconductor layer of the conductivity type opposite to that of theelectroconductive semiconductor layer, in the electroconductivesemiconductor layer, and electrically connect the electroconductivesemiconductor layer to the channel semiconductor portion.

In the production method of the vertical junction field effecttransistor, preferably, the step of forming the drift semiconductorlayer comprises forming the drift semiconductor layer so as to form anon-electroconductive semiconductor layer of the conductivity typeopposite to that of the drift semiconductor portion, form anelectroconductive semiconductor layer of the conductivity type oppositeto that of the non-electroconductive semiconductor layer, in thenon-electroconductive semiconductor layer, and electrically connect theelectroconductive semiconductor layer to the channel semiconductorportion.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a perspective view of a vertical JFET in the firstembodiment. FIG. 1B is a sectional view along I-I line of the verticalJFET in the first embodiment.

FIG. 2A is a perspective view in a drain semiconductor film formingstep. FIG. 2B is a perspective view in a drift semiconductor filmforming step. FIG. 2C is a perspective view in a buried semiconductorportion forming step.

FIG. 3A is a perspective view in a channel semiconductor film formingstep. FIG. 3B is a perspective view in a source semiconductor filmforming step.

FIG. 4A is a perspective view in a source semiconductor portion formingstep. FIG. 4B is a perspective view in a p⁺ type semiconductor regionforming step.

FIG. 5A is a perspective view in a p⁺ type semiconductor portion formingstep. FIG. 5B is a perspective view in a thermal oxidation step.

FIG. 6A is a perspective view in an aperture forming step. FIG. 6B is aperspective view in an electrode forming step.

FIG. 7A is a perspective view in a shallow recess forming step. FIG. 7Bis a perspective view in a deep recess forming step.

FIG. 8 is a perspective view in a gate semiconductor portion formingstep.

FIG. 9 is a perspective view of a vertical JFET in the fourthembodiment.

FIG. 10 is a perspective view of a vertical JFET in the fourthembodiment.

FIG. 11A is a perspective view in a p⁺ type semiconductor film formingstep. FIG. 11B is a perspective view in a source semiconductor filmforming step. FIG. 11C is a perspective view in a p⁺ type semiconductorportion forming step.

FIG. 12 is a perspective view of a vertical JFET in the sixthembodiment.

FIG. 13A is a perspective view of a vertical JFET in the seventhembodiment. FIG. 13B is a sectional view along II-II line of thevertical JFET in the seventh embodiment.

FIG. 14A is a perspective view in a p⁺ type semiconductor layer formingstep. FIG. 14B is a perspective view in a p⁺ type connectionsemiconductor layer forming step.

FIG. 15A is a perspective view in a p⁺ type gate semiconductor portionforming step. FIG. 15B is a perspective view in a p⁺ type gatesemiconductor portion forming step.

FIG. 16A is a perspective view in a channel semiconductor film formingstep. FIG. 16B is a perspective view in a source semiconductor filmforming step.

FIG. 17A is a perspective view in a source semiconductor portion formingstep. FIG. 17B is a perspective view in a thermal oxidation step.

FIG. 18A is a perspective view in an aperture forming step. FIG. 18B isa perspective view in an electrode forming step.

FIG. 19A is a perspective view of a vertical JFET in the ninthembodiment. FIG. 19B is a sectional view along III-III line of thevertical JFET in the ninth embodiment.

FIG. 20A is a perspective view in a second p⁺ type semiconductor layerforming step. FIG. 20B is a perspective view in a p⁺ type connectionsemiconductor layer forming step.

FIG. 21A is a perspective view of a vertical JFET in the eleventhembodiment. FIG. 21B is a perspective view of a pulse-dopedsemiconductor portion of the vertical JFET in the eleventh embodiment.

FIG. 22A is a perspective view of a vertical JFET showing another formhaving the pulse-doped structure. FIG. 22B is a perspective view of avertical JFET showing still another form having the pulse-dopedstructure.

FIG. 23 is a perspective view of a vertical JFET in the twelfthembodiment.

FIG. 24A is a perspective view of a vertical JFET in the twelfthembodiment. FIG. 24B is a perspective view of a vertical JFET in thetwelfth embodiment.

FIG. 25 is a sectional view of a vertical JFET in the thirteenthembodiment.

FIG. 26 is a sectional view of a vertical JFET showing another formhaving the super junction structure.

FIG. 27 is a sectional view of a vertical JFET showing still anotherform having the super junction structure.

FIG. 28A is a schematic view showing a positional relation betweensemiconductor regions and gate semiconductor portions of a vertical JFETin the fourteenth embodiment. FIG. 28B is a schematic view showing avertical JFET in the thirteenth embodiment. FIG. 28C is a schematic viewshowing a vertical JFET in still another form.

FIG. 29A is a perspective view of a vertical JFET in a drift regionforming step. FIG. 29B is a perspective view of a vertical JFET in a p⁺type semiconductor region forming step. FIG. 29C is a perspective viewof a vertical JFET in a source region forming step.

FIG. 30 is a sectional view of a vertical JFET in the sixteenthembodiment.

FIG. 31A is a sectional view in a drain semiconductor film forming step.FIG. 31B is a sectional view in a drift semiconductor film forming step.FIG. 31C is a sectional view in a gate semiconductor portion formingstep.

FIG. 32A is a sectional view in a channel semiconductor film formingstep. FIG. 32B is a sectional view in a source semiconductor filmforming step. FIG. 32C is a sectional view in a source semiconductorportion forming step.

FIG. 33A is a sectional view in a p⁺ type gate semiconductor portionforming step. FIG. 33B is a sectional view in a thermal oxidation step.FIG. 33C is a sectional view in an aperture forming step.

FIG. 34A is a sectional view in a gate electrode forming step. FIG. 34Bis a sectional view in an insulating film forming step. FIG. 34C is asectional view in an aperture forming step.

FIG. 35 is a sectional view in a source electrode forming step.

FIG. 36 is a sectional view of a vertical JFET in the eighteenthembodiment.

FIG. 37A is a sectional view in a channel semiconductor film formingstep. FIG. 37B is a sectional view in an n⁻ type semiconductor filmforming step. FIG. 37C is a sectional view in a source semiconductorportion forming step.

FIG. 38 is a perspective view of a vertical JFET in the twentiethembodiment.

FIG. 39 is a sectional view of a vertical JFET in the twenty firstembodiment.

FIG. 40A is a sectional view in a p⁺ type gate semiconductor portionforming step. FIG. 40B is a sectional view after formation of a p⁺ typegate semiconductor portion.

FIG. 41 is a sectional view of a vertical JFET in the twenty thirdembodiment.

FIG. 42A is a sectional view of a vertical JFET in the twenty fourthembodiment. FIG. 42B is a sectional view along III-III line of thevertical JFET in the twenty fourth embodiment.

FIG. 43A is a sectional view of a vertical JFET in the twenty fifthembodiment. FIG. 43B is a sectional view of a pulse-doped semiconductorportion of the vertical JFET in the twenty fifth embodiment.

FIG. 44 is a sectional view of a vertical JFET in the twenty sixthembodiment.

FIG. 45 is a sectional view of a vertical JFET showing another formhaving the super junction structure.

FIG. 46 is a sectional view of a vertical JFET showing still anotherform having the super junction structure.

FIG. 47A is a schematic view showing a positional relation betweensemiconductor regions and gate semiconductor portions of a vertical JFETin the twenty seventh embodiment. FIG. 47B is a schematic view showing avertical JFET in the twenty seventh embodiment. FIG. 47C is a schematicview showing a vertical JFET in still another form.

FIG. 48A is a perspective view of a vertical JFET in a drift regionforming step. FIG. 48B is a perspective view of a vertical JFET in a p⁺type semiconductor region forming step. FIG. 48C is a perspective viewof a vertical JFET in a source region forming step.

BEST MODES FOR CARRYING OUT THE INVENTION

The preferred embodiments of vertical junction field effect transistorsaccording to the present invention will be described below in detailwith reference to the accompanying drawings. Identical or equivalentelements will be denoted by the same reference symbols throughout thedescription below, without redundant description. It is also noted thataspect ratios of transistors in the drawings do not always agree withthose of actual transistors.

(First Embodiment) FIG. 1A is a perspective view of a vertical JFET 1 ain the first embodiment. As shown in FIG. 1A, the vertical JFET 1 a hasan n⁺ type drain semiconductor portion 2, an n-type drift semiconductorportion 3, a p⁺ type buried semiconductor portion 4, an n-type channelsemiconductor portion 5, an n⁺ type source semiconductor portion 7, anda p⁺ type gate semiconductor portion 8.

The vertical JFET 1 a has a vertical structure in which the majoritycarriers migrate in a direction from one surface to the other surface ofthis device (hereinafter referred to as a “current direction”). FIG. 1Ashows a coordinate system. This coordinate system is defined so that thecurrent direction of the channel portion of the JFET is aligned with they-axis.

The n⁺ type drain semiconductor portion 2 has a pair of surfaces opposedto each other. The n⁺ type drain semiconductor portion 2 can be asubstrate doped with a dopant and, in a preferred example, thissubstrate is made of SiC (silicon carbide). The dopant to be added toSiC can be one of donor impurities such as N (nitrogen), P (phosphorus),and As (arsenic) which are elements of Group 5 in the periodic table.The n⁺ type drain semiconductor portion 2 has a drain electrode 2 a onone (back surface) of a pair of surfaces. The drain electrode 2 a ismade of metal.

The n-type drift semiconductor portion 3 is placed on the other (frontsurface) of the pair of surfaces of the n⁺ type drain semiconductorportion 2. The n-type drift semiconductor portion 3 has first to fourthregions 3 a, 3 b, 3 c, and 3 d arranged in order in the y-axis directionon its front surface. Each of the first to fourth regions 3 a, 3 b, 3 c,and 3 d extends in a predetermined axial direction (the x-axis directionin FIG. 1A) and, in a preferred example, each region is rectangular. Thep⁺ type buried semiconductor portion 4 is placed on the first, second,and third regions 3 a, 3 b, and 3 c. The channel semiconductor portion 5is placed on the fourth region 3 d. The conductivity type of the driftsemiconductor portion 3 is the same as that of the drain semiconductorportion 2, and the dopant concentration of the drift semiconductorportion 3 is lower than that of the drain semiconductor portion 2. In apreferred example, the drift semiconductor portion 3 is made of SiC(silicon carbide) doped with a dopant.

The p⁺ type buried semiconductor portion 4 is placed on the first,second, and third regions 3 a, 3 b, and 3 c. The conductivity type ofthe buried semiconductor portion 4 is opposite to that of the driftsemiconductor portion 3. The p-type dopant concentration of the buriedsemiconductor portion 4 is higher than the n-type dopant concentrationof the drift semiconductor portion 3. In a preferred example, the p⁺type buried semiconductor portion 4 is made of SiC (silicon carbide)doped with a dopant. This dopant can be one of acceptor impurities suchas B (boron) and Al (aluminum) which are elements of Group 3 in theperiodic table.

The n-type channel semiconductor portion 5 is placed on the p⁺ typeburied semiconductor portion 4 and the first to third regions 3 a, 3 b,3 c and on the fourth region 3 d. The n-type channel semiconductorportion 5 extends in a predetermined axial direction (the y-axisdirection in FIG. 1A) along the p⁺ type buried semiconductor portion 4.The n-type channel semiconductor portion 5 is electrically connected tothe n-type drift semiconductor portion 3 in the fourth region 3 d. Sincethe conductivity type of the channel semiconductor portion 5 is oppositeto that of the buried semiconductor portion 4, a pn junction is createdat the interface between the buried semiconductor portion 4 and thechannel semiconductor portion 5. The dopant concentration of the n-typechannel semiconductor portion 5 is lower than that of the n⁺ type drainsemiconductor portion 2. In a preferred example, the n-type channelsemiconductor portion 5 is made of SiC doped with a dopant.

The n⁺ type source semiconductor portion 7 is placed on the n-typechannel semiconductor portion 5 and the first region 3 a. The sourcesemiconductor portion 7 has the same conductivity type as the drainsemiconductor portion 2. The source semiconductor portion 7 is connectedthrough the channel semiconductor portion 5 to the drift semiconductorportion 3. A source electrode 7 a is placed on the n⁺ type sourcesemiconductor portion 7. The source electrode 7 a is made of metal. Aninsulating film 9 such as a silicon oxide film is placed on the n-typesource semiconductor portion 7 and the n-type source semiconductorportion 7 is connected through an aperture of the insulating film 9 tothe source electrode 7 a.

The p⁺ type gate semiconductor portion 8, as shown in FIG. 1B, is placedon the channel semiconductor portion 5 and the third and fourth regions3 c, 3 d. The p⁺ type gate semiconductor portion 8 has projections 8 b,8 c, and 8 d extending in the direction from the third region 3 c towardthe fourth region 3 d (the y-axis direction in the drawing). Theprojections 8 b, 8 c, and 8 d extend so as to reach the buriedsemiconductor portion 4. The projections 8 b, 8 c, 8 d are electricallyconnected to the buried semiconductor portion 4 on the third region 3 c.The n-type channel semiconductor portion 5 is placed between theprojections 8 b, 8 c, 8 d. Since the conductivity type of the gatesemiconductor portion 8 is opposite to that of the channel semiconductorportion 5, a pn junction is created at the interface between the gatesemiconductor portion 8 and the channel semiconductor portion 5. Thedrain current flowing in the n-type channel semiconductor portion 5 iscontrolled by the p⁺ type buried semiconductor portion 4 and the p⁺ typegate semiconductor portion 8. The p-type dopant concentration of thegate semiconductor portion 8 is higher than the n-type dopantconcentration of the channel semiconductor portion 5. In a preferredexample, the p⁺ type gate semiconductor portion 8 is made of SiC dopedwith a dopant. In a preferred example, the channel length (in the y-axisdirection in the drawing) is larger than ten times the channel thickness(in the z-axis direction in the drawing). A gate electrode 8 a is placedon a front surface of the p⁺ type gate semiconductor portion 8. The gateelectrode 8 a is made of metal. The source electrode 7 a is made ofmetal. The insulating film 9 such as a silicon oxide film is placed onthe p⁺ type gate semiconductor portion 8 and the p⁺ type gatesemiconductor portion 8 is connected through an aperture of theinsulating film 9 to the gate electrode 8 a. Arrows e indicate paths ofelectric current flowing from the source semiconductor portion 7 to thedrain semiconductor portion 2.

(Second Embodiment) Next, a production method of the vertical JFET 1 awill be described. FIGS. 2A-2C, FIGS. 3A and 3B, FIGS. 4A and 4B, FIGS.5A and 5B, FIGS. 6A and 6B, FIGS. 7A and 7B, and FIG. 8 are perspectiveviews showing production steps of the vertical JFET 1 a in the secondembodiment.

(Drain Semiconductor Film Forming Step) First, a substrate is preparedas shown in FIG. 2A. An example of the substrate is an n⁺ type SiCsemiconductor substrate. The dopant concentration of the substrate is ashigh as this substrate can be used as the drain semiconductor portion 2.

(Drift Semiconductor Film Forming Step) As shown in FIG. 2B, an SiC film3 is grown on the front surface of the n⁺ type drain semiconductorportion 2 by epitaxial growth. The thickness T1 of the SiC film 3 is,for example, 10 μm. The conductivity type of the SiC film 3 is the sameas that of the n⁺ type drain semiconductor portion 2. The dopantconcentration of the SiC film 3 is lower than that of the n⁺ type drainsemiconductor portion 2. The dopant concentration of the SiC film 3 is,for example, approximately 1×10¹⁶/cm³. The n-type drift semiconductorportion is formed from this SiC film 3.

(Buried Semiconductor Portion Forming Step) A step of forming a buriedsemiconductor portion will be described with reference to FIG. 2C. Amask M1 having a pattern extending in a predetermined axial direction(the x-axis direction in the drawing) is formed. Using this mask M1, anarea 3 e formed on the SiC film 3 is selectively ion-implanted with adopant A1 to form the p⁺ type buried semiconductor portion 4 with apredetermined depth. The depth D1 of the p⁺ type buried semiconductorportion 4 is, for example, approximately 1.2 μm. The dopantconcentration of the p⁺ type buried semiconductor portion 4 is, forexample, approximately 1×10¹⁸/cm³. After the buried semiconductorportion is formed, the mask M1 is removed.

(Channel Semiconductor Film Forming Step) As shown in FIG. 3A, an SiCfilm 5 is grown on the front surface of the p⁺ type buried semiconductorportion 4 and on the SiC film 3 by epitaxial growth. The thickness T2 ofthe SiC film 5 is, for example, approximately 0.5 μm. The conductivitytype of the SiC film 5 is the same as that of the drain semiconductorportion 2. The dopant concentration of the SiC film 5 is lower than thatof the drain semiconductor portion 2. The dopant concentration of theSiC film 5 is, for example, approximately 1×10¹⁷/cm³. The n-type channelsemiconductor portion is formed from this SiC film 5. Although in thepresent embodiment a single SiC film is formed for each of the n-typedrift semiconductor portion and the n-type channel semiconductorportion, the production method may include a plurality of film-formingsteps of repeatedly forming SiC films for each of the driftsemiconductor portion and the channel semiconductor portion. A desireddopant concentration profile can be adopted for the SiC film so that theSiC film 3 can serve as the drift semiconductor portion and the channelsemiconductor portion.

(Source Semiconductor Film Forming Step) As shown in FIG. 3B, an SiCfilm 7 for the n⁺ type source semiconductor portion is grown on thefront surface of the SiC film 5 by epitaxial growth. The thickness T3 ofthe SiC film 7 is, for example, approximately 0.2 μm. The conductivitytype of the SiC film 7 is the same as that of the drain semiconductorportion 2. The dopant concentration of the SiC film 7 is higher thanthat of the SiC film 5.

(Source Semiconductor Portion Forming Step) A step of forming a sourcesemiconductor portion will be described with reference to FIG. 4A. Amask M2 having a pattern extending in a predetermined axial direction(the x-axis direction in the drawing) is formed. Using the mask M2, then⁺ type source film 7 and the SiC film 5 are selectively etched. As aresult, the part of the n⁺ type source layer 7 and SiC film 5 covered bythe mask M2 remains unetched, to form a semiconductor portion for the n⁺type source semiconductor portion. After this semiconductor portion isformed, the mask M2 is removed.

(p⁺ Type Semiconductor Region Forming Step) A step of forming p⁺ typesemiconductor regions will be described with reference to FIG. 4B. Amask M3 having a pattern of a predetermined shape is formed. Regions 5a, 5 b, and 5 c defined on the SiC film 5 by the mask M3 are selectivelyion-implanted with a dopant A2 to form p⁺ type semiconductor regions 81,82, and 83 with a predetermined depth. The dopant concentration of thep⁺ type semiconductor regions 81, 82, 83 is, for example, approximately1×10¹⁸/cm³. After the p⁺ type semiconductor regions are formed, the maskM3 is removed.

(p⁺ Type Semiconductor Portion Forming Step) A step of forming a p⁺ typesemiconductor portion will be described with reference to FIG. 5A. Amask M4 having a pattern of a predetermined shape is formed. Regionsdefined on the SiC film 5 by the mask M4 (e.g., regions 5 a-5 eincluding the regions 5 a-5 c) are selectively ion-implanted with adopant A3 to form p⁺ type semiconductor layers 84, 85 with apredetermined depth. The dopant concentration of the p⁺ typesemiconductor layers 84, 85 is, for example, approximately 1×10¹⁸/cm³.The concentration in the vicinity of the front surface is approximately1×10¹⁹ to 1×10²⁰/cm³. After the p⁺ type semiconductor layers are formed,the mask M4 is removed. The sequence of the p⁺ type semiconductor layerforming step and the p⁺ type semiconductor portion forming step isreversible.

(Thermal Oxidation Step) A step of thermally oxidizing the vertical JFET1 a will be described with reference to FIG. 5B. The vertical JFET 1 ais subjected to a thermal oxidation treatment. The thermal oxidationtreatment is a treatment of exposing SiC to an oxidizing atmosphere at ahigh temperature (e.g., about 1200° C.) to bring about chemical reactionof silicon in each semiconductor portion with oxygen to form a siliconoxide film (SiO₂). As a result, the front surface of each semiconductorportion is covered by an oxide film 9.

(Aperture Forming Step) A step of forming apertures for formation of thesource electrode and the gate electrode will be described with referenceto FIG. 6A. The oxide film 9 is selectively etched using a mask of aphotoresist, to form apertures 9 a, 9 b. Front surface portions of thesource semiconductor portion 7 and the gate semiconductor portion 8 areexposed in the respective apertures 9 a, 9 b. These exposed parts serveas conducting portions one to the source electrode and the other to thegate electrode. After the apertures are formed, the resist mask isremoved.

(Electrode Forming Step) A step of forming electrodes will be describedwith reference to FIG. 6B. First, a metal film for ohmic contactelectrodes, e.g., nickel (Ni) is deposited on the front surface of thevertical JFET 1 a. Next, a mask of a photoresist is formed so as toleave Ni in the source-electrode aperture 9 a and the gate-electrodeaperture 9 b only, the Ni metal film is etched, and the resist isremoved. Subsequently, ohmic contacts are created by thermally treatingthe film in an inert gas atmosphere such as nitrogen or argon at a hightemperature (e.g., about 1000° C. in the case of Ni). The material ofthe metal film for ohmic contact electrodes may be one of Ni, tungsten(W), and titanium (Ti), but the material is not limited to these.

Furthermore, a metal film for electrodes such as aluminum (Al) isdeposited. A mask of a photoresist having a predetermined shape isformed. The metal film for electrodes is selectively etched using thismask. As a result, the parts of the metal film for electrodes covered bythe resist pattern remain unetched, to obtain the source electrode 7 aand gate electrode 8 a. The material of the metal film for electrodesmay be one of aluminum alloys, copper (Cu), and tungsten (W), but thematerial is not limited to these. After the electrodes are formed, theresist mask is removed.

The vertical JFET 1 a described in the first embodiment is completedthrough the steps described above. In the structure of the vertical JFET1 a, the p⁺ type buried semiconductor portion 4 and the p⁺ type gatesemiconductor portion 8 can be arranged on the n-type driftsemiconductor portion 3. Therefore, a desired drain blocking voltage canbe achieved by the thickness of the n-type drift semiconductor portion3, without increasing the chip size. Accordingly, the breakdown voltagebetween the source and the drain can be improved. Carriers flow not onlyunder the n-type channel semiconductor portion 5, but also in the n-typedrift semiconductor portion 3 located below the p⁺ type buriedsemiconductor portion 4. It is thus feasible to lower the on-stateresistance while maintaining the breakdown voltage. Namely, thisstructure is suitable for high-breakdown-voltage JFETs.

In the vertical JFET 1 a, the n-type channel semiconductor portion 5 isplaced between the p⁺ type buried semiconductor portion 4 and the p⁺type gate semiconductor portion 8 and the n-type channel semiconductorportion 5 is also placed between the projections of the p⁺ type gatesemiconductor portion 8. This structure increases the width of thecontrollable channel, as compared with a case where the channel iscontrolled from one side of the n-type channel semiconductor portion 5.Where the space A between the p⁺ type buried semiconductor portion 4 andthe p⁺ type gate semiconductor portion 8 is wider than the space Bbetween the projections of the p⁺ type gate semiconductor portion 8, thethreshold of the vertical JFET 1 a is determined by the space B.Conversely, where the space A between the p⁺ type buried semiconductorportion 4 and the p⁺ type gate semiconductor portion 8 is narrower thanthe space B between the projections of the p⁺ type gate semiconductorportion 8, the threshold of the vertical JFET 1 a is determined by thespace A.

In the present embodiment the semiconductor portions of the drain,source, and gate are made of SiC. SiC is superior in the followingrespects to such semiconductors as Si (silicon) and GaAs (galliumarsenide). Namely, since SiC has a high melting point and a largebandgap (forbidden band width), it facilitates operation at hightemperatures of the device. Since SiC has a large breakdown electricfield, it enables achievement of high breakdown voltage. Furthermore, ithas the advantage of facilitating achievement of large electric currentand low loss by virtue of its high thermal conductivity.

(Third Embodiment) The present embodiment relates to a production methoddifferent from the second embodiment, in the p⁺ type semiconductor layerforming step and the p⁺ type semiconductor portion forming step of thevertical JFET 1 a. Namely, the second embodiment involved the formationof the gate semiconductor portion 8 by ion implantation, whereas thepresent embodiment involves formation of the gate semiconductor portion8 through the steps described below. The description and illustrationwill be omitted for the steps except for the p⁺ type semiconductor layerforming step and the p⁺ type semiconductor portion forming step.Constitutive portions similar to those in the second embodiment aredenoted by the same reference symbols.

(Shallow Recess Forming Step) A step of forming a shallow recess in then-type semiconductor layer 5 will be described with reference to FIG.7A. The shallow recess forming step is carried out in succession to thesource semiconductor portion forming step of the second embodiment. Aphotoresist mask M5 having a pattern of a predetermined shape is formed.The n-type semiconductor layer 5 is selectively etched using the maskM5. The etching depth D5 is so large as not to reach the p⁺ type buriedsemiconductor portion 4. As a result, the part of the n-typesemiconductor layer 5 covered by the resist pattern remains unetched, toform a shallow recess. After the shallow recess is formed, the mask M5is removed.

(Deep Recess Forming Step) A step of forming deep recesses in the n-typesemiconductor layer 5 will be described with reference to FIG. 7B. Aphotoresist mask M6 having a pattern of a predetermined shape is formed.The n-type semiconductor layer 5 is selectively etched using the maskM6. The etching depth D6 is so large as to reach the p⁺ type buriedsemiconductor portion 4. As a result, the part of the n-typesemiconductor layer 5 covered by the resist pattern remains unetched, soas to form deep recesses of stripe shape extending in a predeterminedaxial direction (the y-axis direction in the drawing). After the deeprecesses are formed, the mask M6 is removed.

(Gate Semiconductor Portion Forming Step) A step of forming a gatesemiconductor portion will be described with reference to FIG. 8.Polysilicon is deposited on the front surfaces of the n-type driftsemiconductor layer 3, the p⁺ type buried semiconductor layer 4, and then-type semiconductor layer 5 to form a polysilicon semiconductor portion8 in the shallow recess and the deep recesses. The polysilicon filmgrows, for example, through thermal decomposition of SiH₄ (silane) bychemical vapor deposition. The conductivity type of the polysiliconsemiconductor portion 8 is opposite to that of the drain semiconductorportion 2. The dopant concentration of the polysilicon semiconductorportion 8 is higher than that of the n-type semiconductor layer 5. Thethermal oxidation step and subsequent steps are carried out insuccession to the gate semiconductor portion forming step. According tothe production method described in the third embodiment, the channelsemiconductor portion and the gate semiconductor portion can be formedas a heterojunction.

(Fourth Embodiment) The vertical JFET 1 a described in the firstembodiment can have a modification form as shown in FIG. 9. FIG. 9 is aperspective view of a vertical JFET 1 c in the fourth embodiment.Namely, the vertical JFET 1 c in the fourth embodiment has a p⁺ typesemiconductor portion 6 on the p⁺ type buried semiconductor portion 4and fifth region 3 e.

The vertical JFET 1 b described in the first embodiment can also have amodification form as shown in FIG. 10. FIG. 10 is a perspective view ofa vertical JFET 1 d in the fourth embodiment. Namely, the vertical JFET1 d in still another embodiment has a p⁺ type semiconductor portion 6 onthe p⁺ type buried semiconductor portion 4 and fifth region 3 e.

In the vertical JFETs 1 c, 1 d, the n-type drift semiconductor portion 3has first to fifth regions 3 e, 3 a, 3 b, 3 c, and 3 d arranged in orderin the y-axis direction, on its front surface. The p⁺ type semiconductorportion 6 is placed on the p⁺ type buried semiconductor portion 4 andfifth region 3 e. The p⁺ type semiconductor portion 6 extends along then-type channel semiconductor portion 5 (in the z-axis direction in thedrawing). The conductivity type of the semiconductor portion 6 isopposite to that of the channel semiconductor portion 5. The p-typedopant concentration of the semiconductor portion 6 is higher than then-type dopant concentration of the channel semiconductor portion 5. In apreferred example, the p⁺ type semiconductor portion 6 is made of SiCdoped with a dopant.

In the vertical JFETs 1 c, 1 d in the fourth embodiment, the p⁺ typeburied semiconductor portion 4 is electrically connected through the p⁺type semiconductor portion 6 to an electrode 6 a. When the electrode 6 ais used as a gate electrode, a channel semiconductor portion is alsoformed between the p⁺ type semiconductor portion and the p⁺ type buriedsemiconductor portion. It thus becomes feasible to let the electriccurrent flow more and to decrease loss.

In the vertical JFETs 1 c, 1 d in the present embodiment, it is alsopossible to adopt a structure wherein the p⁺ type buried semiconductorportion 4 and the source semiconductor portion 7 are electricallyconnected to the same source electrode 7 a, by connecting the p⁺ typesemiconductor portion 6 to the source electrode 7 a, instead of theelectrode 6 a. This keeps the p⁺ type buried semiconductor portion 4 atthe same potential as the source semiconductor portion 7. At this time,the capacitance between the p⁺ type buried semiconductor portion and thedrain semiconductor portion turns from the gate-drain capacitance to thegate-source capacitance, so as to enable high-frequency operation.

(Fifth Embodiment) Next, the fifth embodiment, which is a modificationof the second embodiment, will be described with reference to FIGS. 11Ato 11C. For a production method of a vertical JFET in the fifthembodiment, constitutive elements similar to those in the productionmethod of the vertical JFET 1 a described in the second embodiment aredenoted by the same reference symbols. The p⁺ type semiconductor filmforming step and the steps subsequent thereto different from the secondembodiment will be described below.

(p⁺ Type Semiconductor Film Forming Step) A step of forming a p⁺ typesemiconductor film will be described with reference to FIG. 11A. The p⁺type semiconductor film forming step is carried out in succession to thechannel semiconductor film forming step. A mask M7 having a pattern of apredetermined shape is formed. Using the mask M7, a region 51 a formedon an SiC film 51 is selectively ion-implanted with a dopant 4A to forma p⁺ type semiconductor layer 61. The thickness T4 of the SiC film 51 isone that permits a p⁺ type semiconductor layer 61 reaching the p⁺ typegate semiconductor portion 4, to be formed by ion implantation. Thedopant concentration of the p⁺ type semiconductor layer 61 isapproximately equal to that of the p⁺ type gate semiconductor portion 4.After the p⁺ type semiconductor layer 61 is formed, the mask M7 isremoved. The channel semiconductor film forming step and the p⁺ typesemiconductor film forming step are repeatedly carried out until thechannel semiconductor film and the p⁺ type semiconductor film come tohave a predetermined thickness.

(Source Semiconductor Film Forming Step) As shown in FIG. 11B, an SiCfilm 7 for the n⁺ type source layer is formed on the n-typesemiconductor layer 5 and on the p⁺ type semiconductor layer 6 byepitaxial growth. The conductivity type of the SiC film 7 is the same asthat of the n⁺ type drain semiconductor portion 2. The dopantconcentration of the SiC film 7 is higher than that of the SiC film 5.

(p⁺ Type Semiconductor Portion Forming Step) A step of forming a p⁺ typesemiconductor portion will be described with reference to FIG. 11C. Amask M8 having a pattern of a predetermined shape is formed. Using themask M8, a region 7 a formed on the SiC film 7 is selectivelyion-implanted with a dopant AS to form a p⁺ type semiconductor portion6. After the p⁺ type semiconductor portion 6 is formed, the mask M8 isremoved. The source semiconductor portion forming step is carried out insuccession to the p⁺ type semiconductor portion forming step. The abovedescribed the p⁺ type semiconductor film forming step and the stepssubsequent thereto, different from the second embodiment. The othersteps are similar to those in the second embodiment, but are not limitedto this.

(Sixth Embodiment) The vertical JFET 1 a described in the fourthembodiment can also have a modification form as shown in FIG. 12. FIG.12 is a perspective view of a vertical JFET 1 e in the sixth embodiment.Namely, the fourth embodiment employed the configuration wherein then-type channel semiconductor portion 5 was in contact with the n⁺ typesource semiconductor portion 7 above the first region 3 a. In contrastto it, the sixth embodiment employs a configuration wherein the verticalJFET 1 e further has an n⁻ type semiconductor portion 10 between then-type channel semiconductor portion 5 and the n⁺ type sourcesemiconductor portion 7. The present embodiment is particularly suitablefor forms wherein the space between the p⁺ type gate semiconductorportion 4 and the n⁻ type semiconductor portion 10 is smaller than thespace between the projections of the p⁺ type gate semiconductor portion8.

The n⁻ type semiconductor portion 10 is placed on the n-type channelsemiconductor portion 5 and the first to fourth regions 3 a, 3 b, 3 c, 3d. The conductivity type of the semiconductor portion 10 is the same asthat of the channel semiconductor portion 5. The n-type dopantconcentration of the semiconductor portion 10 is lower than the n-typedopant concentration of the channel semiconductor portion 5. The dopantconcentration of the n⁻ type semiconductor portion 10 is, for example,approximately 1×10¹⁶/cm³. In a preferred example, the n⁻ typesemiconductor portion 10 is made of SiC (silicon carbide) doped with adopant.

Since this structure keeps the n-type channel semiconductor portion 5unetched, the thickness of the channel semiconductor portion is notaffected by variations due to the etching step. Therefore, it isfeasible to reduce individual differences in electrical characteristicsamong vertical JFETs 1 e.

In the vertical JFET 1 e in the present embodiment, it is also possibleto adopt a structure wherein the p⁺ type buried semiconductor portion 4and the source semiconductor portion 7 are electrically connected to thesame source electrode 7 a, by connecting the p⁺ type semiconductorportion 6 to the source electrode 7 a, instead of the electrode 6 a.This keeps the p⁺ type buried semiconductor portion 4 at the samepotential as the source semiconductor portion 7, whereby the capacitancebetween the p⁺ type buried semiconductor portion and the drainsemiconductor portion turns from the gate-drain capacitance to thegate-source capacitance, so as to enable high-frequency operation.

(Seventh Embodiment) Next, the seventh embodiment, which is amodification of the first embodiment, will be described with referenceto FIG. 13A. For a vertical JFET in the seventh embodiment, constitutiveelements similar to those in the configuration of the vertical JFET 1 adescribed in the first embodiment are denoted by the same referencesymbols. A configuration of the channel semiconductor portion differentfrom the first embodiment will be described below.

FIG. 13A is a perspective view of a vertical JFET 1 f in the seventhembodiment. The seventh embodiment is different in the structure of thechannel semiconductor portion from the first embodiment. As shown inFIG. 13A, the vertical JFET 1 f has an n⁺ type drain semiconductorportion 2, an n-type drift semiconductor portion 3, a p⁺ type gatesemiconductor portion 4, an n-type channel semiconductor portion 5, ann⁺ type source semiconductor portion 7, p⁺ type gate semiconductorportions 81, 82, and 83, and a p⁺ type connection semiconductor portion11.

The n-type channel semiconductor portion 5 has n-type channelsemiconductor regions 51, 52, and 53. The n-type channel semiconductorregion 51 is placed on the p⁺ type gate semiconductor portion 4 and thesecond to fourth regions 3 b, 3 c, and 3 d of the n-type driftsemiconductor portion 3. The n-type channel semiconductor region 51 isprovided between the p⁺ type gate semiconductor portion 4 and the p⁺type gate semiconductor portion 81, between the p⁺ type gatesemiconductor portions 81 and 82, and between the p⁺ type gatesemiconductor portions 82 and 83. The n-type channel semiconductorregion 52 is placed on the fifth region 3 e of the n-type driftsemiconductor portion 3 and is connected to the n-type driftsemiconductor portion 3 in the fifth region 3 e. The n-type channelsemiconductor region 53 is placed above the first region 3 a of then-type drift semiconductor portion 3. The n-type channel semiconductorregion 53 is connected through the n-type channel semiconductor region51 to the n-type channel semiconductor region 52.

The dopant concentration of the n-type channel semiconductor portion 5is lower than that of the n⁺ type drain semiconductor portion 2. In apreferred example, the n-type channel semiconductor portion 5 is made ofSiC doped with a dopant.

The p⁺ type gate semiconductor portions 81, 82, and 83 are placed abovethe second to fourth regions 3 b-3 d. The n-type channel semiconductorregion 51 is placed between the p⁺ type gate semiconductor portions 81,82, 83. Since the conductivity type of the gate semiconductor portions81, 82, 83 and the gate semiconductor portion 4 is opposite to that ofthe channel semiconductor region 51, a pn junction is created at eachinterface between the gate semiconductor portions 81, 82, 83, 4 and thechannel semiconductor region 51. The drain current flowing in the n-typechannel semiconductor region 51 is controlled by the p⁺ type gatesemiconductor portions 81, 82, 83, 4. The p-type dopant concentration ofthe gate semiconductor portions 81, 82, 83, and 4 is higher than then-type dopant concentration of the channel semiconductor region 51. In apreferred example, the p⁺ type gate semiconductor portions 81, 82, 83,and 4 are made of SiC doped with a dopant. A gate electrode 8 a isplaced on the front surface of the p⁺ type gate semiconductor portion83. The gate electrode 8 a is made of metal. An insulating film 9 suchas a silicon oxide film is placed on the p⁺ type gate semiconductorportion 83, and the p⁺ type gate semiconductor portion 83 is connectedthrough an aperture of the insulating film 9 to the gate electrode 8 a.

The p⁺ type connection semiconductor portion 11, as shown in FIG. 13B,is placed above the third region 3 c. The conductivity type of theconnection semiconductor portion 11 is the same as that of the gatesemiconductor portion 4. The p⁺ type connection semiconductor portion 11extends in the vertical direction (the z-axis direction in the drawing)to connect the p⁺ type gate semiconductor portion 4 and the p⁺ type gatesemiconductor portions 81, 82, 83. The p-type dopant concentration ofthe connection semiconductor portion 11 is higher than the n-type dopantconcentration of the channel semiconductor region 51. In a preferredexample, the p⁺ type connection semiconductor portion 11 is made of SiCdoped with a dopant. Arrows e indicate paths of electric current flowingfrom the source semiconductor portion 7 to the drain semiconductorportion 2.

(Eighth Embodiment) Next, the eighth embodiment, which is a modificationof the second embodiment, will be described with reference to FIGS. 14Aand 14B, FIGS. 15A and 15B, FIGS. 16A and 16B, FIGS. 17A and 17B, andFIGS. 18A and 18B. For a production method of a vertical JFET in theeighth embodiment, constitutive elements similar to those in theproduction method of the vertical JFET 1 a described in the secondembodiment are denoted by the same reference symbols. The channelsemiconductor film forming step and the steps subsequent thereto,different from the second embodiment, will be described below.

(p⁺ Type Semiconductor Layer Forming Step) A step of forming a p⁺ typesemiconductor layer will be described with reference to FIG. 14A. The p⁺type semiconductor layer forming step is carried out in succession tothe channel semiconductor film forming step. A mask M9 having a patternextending in a predetermined direction (the x-axis direction in thedrawing) is formed. Using the mask M9, a region 51 a defined on the SiCfilm 51 is selectively ion-implanted with a dopant A6 to form a p⁺ typesemiconductor layer 81. The depth D7 of ion implantation is determinedaccording to the threshold of the vertical JFET. After the p⁺ typesemiconductor layer is formed, the mask M9 is removed.

(p⁺ Type Connection Semiconductor Layer Forming Step) A step of forminga p⁺ type connection semiconductor layer will be described withreference to FIG. 14B. A mask M10 having a pattern of a predeterminedshape is formed. Using the mask M10, a region 51 b defined on the SiCfilm 51 is selectively ion-implanted with a dopant A7 to form a p⁺ typeconnection semiconductor layer 111. The depth of ion implantation is sodeep as to reach the p⁺ type gate semiconductor portion 4. The dopantconcentration of the p⁺ type connection semiconductor layer 111 isapproximately equal to that of the p⁺ type gate semiconductor portion 4.After the p⁺ type semiconductor layer is formed, the mask M10 isremoved.

(p⁺ Type Gate Semiconductor Portion Forming Step) A step of forming a p⁺type gate semiconductor portion will be described with reference toFIGS. 15A and 15B. This step involves repetitions of the channelsemiconductor film forming step, the p⁺ type semiconductor layer formingstep, and the p⁺ type connection semiconductor layer forming step todeposit the semiconductor layers having the p⁺ type semiconductor layerand the p⁺ type connection semiconductor layer on the n-type driftsemiconductor portion 3, thereby forming a stack type channel portion.As a result, the semiconductor layer 5 is formed in a predeterminedthickness T5 (in the z-axis direction in the drawing).

(Channel Semiconductor Film Forming Step) A step of forming an n-typechannel semiconductor film will be described with reference to FIG. 16A.As shown in FIG. 16A, an SiC film 54 is grown on the SiC film 5 byepitaxial growth. The conductivity type of the SiC film 54 is the sameas that of the n⁺ type drain semiconductor portion 2. The dopantconcentration of the SiC film 54 is lower than that of the drainsemiconductor portion 2.

(Source Semiconductor Film Forming Step) As shown in FIG. 16B, an SiCfilm 7 for the n⁺ type source layer is formed on the front surface ofthe SiC film 54 by epitaxial growth. The conductivity type of the SiCfilm 7 is the same as that of the drain semiconductor portion 2. Thedopant concentration of the SiC film 7 is higher than that of the SiCfilm 54.

(Source Semiconductor Portion Forming Step) A step of forming a sourcesemiconductor portion will be described with reference to FIG. 17A. Amask M11 having a pattern extending in a predetermined axial direction(the x-axis direction in the drawing) is formed. The n⁺ type sourcelayer 7 and the SiC film 54 are selectively etched using the mask M11.As a result, part 54 a of the n⁺ type source layer 7 and SiC film 54covered by the resist pattern remains unetched, so as to form an n⁺ typesource semiconductor portion 7. After the source semiconductor portionis formed, the mask M11 is removed.

(Thermal Oxidation Step) A step of thermally oxidizing the vertical JFET1 f will be described with is reference to FIG. 17B. The vertical JFET 1f is subjected to a thermal oxidation treatment. The thermal oxidationtreatment is a treatment of exposing SiC to an oxidizing atmosphere at ahigh temperature (e.g., about 1200° C.) to bring about chemical reactionof silicon in each semiconductor portion with oxygen to form a siliconoxide film (SiO₂). This results in covering the front surface of eachsemiconductor portion by the oxide film 9.

(Aperture Forming Step) A step of forming apertures for formation of thesource electrode and gate electrode will be described with reference toFIG. 18A. The oxide film 9 is selectively etched using a mask of aphotoresist, to form apertures 9 a, 9 b. The front surface parts of thesource semiconductor portion 7 and the gate semiconductor portion 8 areexposed in the respective apertures 9 a, 9 b. The exposed portionsbecome conducting portions to the source electrode and to the gateelectrode. After the apertures are formed, the resist mask is removed.

(Electrode Forming Step) A step of forming electrodes will be describedwith reference to FIG. 18B. First, a metal film for ohmic contactelectrodes, e.g., nickel (Ni) is deposited on the front surface of thevertical JFET 1 f. Next, a mask of a photoresist is formed so as toleave Ni in the source-electrode aperture 9 a and the gate-electrodeaperture 9 b only, the Ni metal film is etched, and the resist isremoved. Subsequently, the surface is thermally treated in an inert gasatmosphere such as nitrogen or argon at a high temperature (e.g., about1000° C. in the case of Ni), to form ohmic contacts. The material of themetal film for ohmic contact electrodes may be one of Ni, tungsten (W),and titanium (Ti), but is not limited to these.

Furthermore, a metal film for electrodes such as aluminum (Al) isdeposited. A mask of a photoresist having a predetermined shape isformed. The metal film for electrodes is selectively etched using thismask. As a result, the part of the metal film for electrodes covered bythe resist pattern remains unetched, to form a source electrode 7 a anda gate electrode 8 a. The material of the metal film for electrodes maybe one of aluminum alloys, copper (Cu), and tungsten (W), but is notlimited to these. After the electrodes are formed, the resist mask isremoved.

The vertical JFET 1 f in the seventh embodiment is completed through thesteps described above. In the structure of the vertical JFET 1 f the p⁺type gate semiconductor portions 81, 82, and 83 are connected throughthe p⁺ type connection semiconductor portion 11 to the p⁺ type gatesemiconductor portion 4. This permits the p⁺ type connectionsemiconductor portion 11 and the p⁺ type gate semiconductor portions 81,82, 83 to be used as a gate. It also permits the gate electrode 8 a tobe connected to the buried gate semiconductor portion. Therefore, thechannel region is created between the p⁺ type gate semiconductorportions 4, 81, 82, 83. Accordingly, it is feasible to increase thechannel region that can be controlled by the gate semiconductorportions, and to decrease the on-state resistance.

(Ninth Embodiment) The vertical JFET 1 f described in the seventhembodiment can also have a modification form as shown in FIG. 19A. FIG.19A is a perspective view of a vertical JFET 1 g in the ninthembodiment. Namely, the vertical JFET 1 g in the ninth embodiment isdifferent from the vertical JFET 1 f in that a p⁺ type semiconductorportion 6 is provided on the p⁺ type buried semiconductor portion 4 andthe sixth region 3 f.

In the vertical JFET 1 g, the n-type drift semiconductor portion 3 hasfirst to sixth regions 3 f, 3 a, 3 b, 3 c, 3 d, and 3 e arranged inorder in the y-axis direction, on its front surface. The p⁺ typesemiconductor portion 6 is placed on the p⁺ type buried semiconductorportion 4 and the sixth region 3 f. The p⁺ type semiconductor portion 6extends along the n⁺ type source semiconductor portion 7 (in the x-axisdirection in the drawing). The conductivity type of the p⁺ typesemiconductor portion 6 is opposite to that of the n-type channelsemiconductor portion 5. The p-type dopant concentration of thesemiconductor portion 6 is higher than the n-type dopant concentrationof the channel semiconductor portion 5. In a preferred example, the p⁺type semiconductor portion 6 is made of SiC doped with a dopant.

In the vertical JFET 1 g in the ninth embodiment, the p⁺ type buriedsemiconductor portion 4 is electrically connected through the p⁺ typesemiconductor portion 6 to the electrode 6 a. The electrode 6 a can alsobe used as a gate electrode, and no connection semiconductor portion 11exists in the channel semiconductor portion between the p⁺ type gatesemiconductor portion 81 and the p⁺ type buried semiconductor portion 4.Therefore, the current paths are greater and the on-state resistance issmaller by that degree.

In the vertical JFET 1 g in the present embodiment, it is also possibleto adopt a structure wherein the p⁺ type buried semiconductor portion 4and the source semiconductor portion 7 are electrically connected to thesame source electrode 7 a, by connecting the p⁺ type semiconductorportion 6 to the source electrode 7 a, instead of the electrode 6 a.This keeps the p⁺ type buried semiconductor portion 4 at the samepotential as the source semiconductor portion 7, and the capacitancebetween the p⁺ type buried semiconductor portion and the drainsemiconductor portion turns from the gate-drain capacitance to thegate-source capacitance, so as to enable high-frequency operation.

(Tenth Embodiment) The tenth embodiment, which is a modification of theeighth embodiment, will be described with reference to FIGS. 20A and20B. For a production method of a vertical JFET in the tenth embodiment,constitutive elements similar to those in the production method of thevertical JFET 1 f described in the eighth embodiment are denoted by thesame reference symbols. A p⁺ type semiconductor portion forming stepdifferent from the eighth embodiment will be described below.

(Second p⁺ Type Semiconductor Layer Forming Step) A step of forming a p⁺type semiconductor layer will be described with reference to FIG. 20A.The second p⁺ type semiconductor layer forming step is carried out insuccession to the p⁺ type semiconductor layer forming step. A mask M12having a pattern of a predetermined shape is formed. Using the mask M12,a region 51 c defined on the SiC film 51 is selectively ion-implantedwith a dopant A8 to form a p⁺ type semiconductor layer 61. The depth ofion implantation is so deep as to reach the p⁺ type buried semiconductorportion 4. The dopant concentration of the p⁺ type semiconductor layer61 is approximately equal to that of the p⁺ type buried semiconductorportion 4. After the p⁺ type semiconductor layer is formed, the mask M12is removed.

(p⁺ Type Connection Semiconductor Layer Forming Step) A step of forminga p⁺ type connection semiconductor layer will be described withreference to FIG. 20B. The n-type semiconductor film 52, p⁺ typesemiconductor portion 82, and p⁺ type semiconductor portion 62 areformed prior to the formation of the p⁺ type connection semiconductorlayer. A mask M13 having a pattern of a predetermined shape is formed. Aregion 52 a defined on the n-type semiconductor film 52 by the mask M13is selectively ion-implanted with a dopant A9 to form a p⁺ typeconnection semiconductor portion layer 111. The depth of ionimplantation is so deep as to reach the p⁺ type gate semiconductorportion 81. The dopant concentration of the p⁺ type connectionsemiconductor layer 111 is approximately equal to that of the p⁺ typesemiconductor layer 61. After the p⁺ type connection semiconductor layer111 is formed, the mask M13 is removed.

A channel semiconductor film forming step is carried out in successionto the p⁺ type connection semiconductor layer forming step. The channelsemiconductor film forming step, p⁺ type semiconductor layer formingstep, second p⁺ type semiconductor layer forming step, and p⁺ typeconnection semiconductor layer forming step are repeatedly carried outto form a stacked channel portion on the n-type drift semiconductorportion 3. The above described the second p⁺ type semiconductor layerforming step and the steps subsequent thereto, different from the eighthembodiment. The other steps are similar to those in the eighthembodiment, but are not limited to this.

(Eleventh Embodiment) Next, the eleventh embodiment, which is amodification of the first embodiment, will be described with referenceto FIGS. 21A and 21B. For a vertical JFET in the eleventh embodiment,constitutive elements similar to those in the configuration of thevertical JFET 1 a described in the first embodiment are denoted by thesame reference symbols. Differences from the first embodiment will bedescribed below.

FIG. 21A is a perspective view of a vertical JFET 1 h in the eleventhembodiment. The eleventh embodiment is different in the structure of thechannel semiconductor portion from the first embodiment. Namely, theeleventh embodiment has the channel semiconductor portion of pulse-dopedstructure.

As shown in FIG. 21B, the pulse-doped semiconductor portion 12 iscomprised of an alternate stack of n⁻ type SiC layers 121-124 and n⁺type SiC layers 125-127. The n-type dopant concentration of the SiClayers 121-124 is lower than the n-type dopant concentration of the SiClayers 125-127. The dopant concentration of the n⁻ type SiC layers 121to 124 is, for example, approximately 1×10¹⁶/cm³. The thickness T6 ofthe n⁻ type SiC layers 121-124 is, for example, about 10 nm. The dopantconcentration of the n⁺ type SiC layers 125-127 is 1×10¹⁷/cm³ to1×10¹⁸/cm³. The thickness T7 of the n⁺ type SiC layers 125 to 127 is,for example, about 10 nm. In such structure, carriers migrate in thelow-concentration layers with the greater carrier mobility than in thehigh-concentration layers, so as to increase the electric currentflowing in the channel region. As a result, the on-state resistance canbe reduced.

The pulse-doped structure is also applicable to the channelsemiconductor portion of the vertical JFET 1 f described in the seventhembodiment, as shown in FIG. 22A. The pulse-doped structure is alsoapplicable to the channel semiconductor portion of the vertical JFET 1 gdescribed in the ninth embodiment, as shown in FIG. 22B.

In the vertical JFETs 1 h, 1 k in the present embodiment, it is alsopossible to adopt the structure wherein the p⁺ type buried semiconductorportion 4 and the source semiconductor portion 7 are electricallyconnected to the same source electrode 7 a, by connecting the p⁺ typesemiconductor portion 6 to the source electrode 7 a, instead of theelectrode 6 a. This keeps the p⁺ type buried semiconductor portion 4 atthe same potential as the source semiconductor portion 7, and thecapacitance between the p⁺ type buried semiconductor portion and thedrain semiconductor portion turns from the gate-drain capacitance to thesource-drain capacitance, so as to enable high-frequency operation.

(Twelfth Embodiment) Next, the twelfth embodiment, which is amodification of the first embodiment, will be described with referenceto FIG. 23. For a vertical JFET in the twelfth embodiment, constitutiveelements similar to those in the configuration of the vertical JFET 1 adescribed in the first embodiment are denoted by the same referencesymbols. Differences from the first embodiment will be described below.

FIG. 23 is a perspective view of a vertical JFET 1 n in the twelfthembodiment. The twelfth embodiment is different in the structure of thegate semiconductor portion from the first embodiment. Namely, thetwelfth embodiment is directed to a configuration wherein the verticalJFET 1 n has a p⁺ type semiconductor portion 13 in the gatesemiconductor portion 4. The p⁺ type semiconductor portion 13 is formedbetween the buried semiconductor portion 4 and the channel semiconductorportion 5 or the p⁺ type semiconductor portion 6. The p⁺ typesemiconductor portion 13 is made of SiC doped with Al (aluminum) as adopant. The gate semiconductor portion 4 is made of SiC doped with B(boron) as a dopant. Since the range of B is larger than that of Al, thegate semiconductor portion 4 is formed between the p⁺ type semiconductorportion 13 and the drift semiconductor portion 3. The dopantconcentration of the gate semiconductor portion 4 is smaller than thatof the p⁺ type semiconductor portion 13. In this structure the depletionlayer also lengthens into the gate semiconductor portion 4, which canmake the potential gradient gentler between the gate semiconductorportion and the drift semiconductor portion, so as to alleviateconcentration of the electric field. It results in improving thebreakdown voltage of the vertical JFET.

This structure is also applicable to the gate semiconductor portion ofthe vertical JFET 1 f described in the seventh embodiment, as shown inFIG. 24A. The pulse-doped structure is also applicable to the gatesemiconductor portion of the vertical JFET 1 g described in the ninthembodiment, as shown in FIG. 24B.

This structure can make the dopant concentration of the gatesemiconductor portion 4 smaller than that of the p⁺ type semiconductorportion 13. In this structure the depletion layer also lengthens intothe gate semiconductor portion 4, which can make the potential gradientgentler between the gate semiconductor portion and the driftsemiconductor portion, so as to alleviate concentration of the electricfield. This results in improving the breakdown voltage of the verticalJFET.

In the vertical JFETs in, 1 q in the present embodiment, it is alsopossible to adopt the structure wherein the p⁺ type buried semiconductorportion 4 and the source semiconductor portion 7 are electricallyconnected to the same source electrode 7 a, by connecting the p⁺ typesemiconductor portion 6 to the source electrode 7 a, instead of theelectrode 6 a. This keeps the p⁺ type buried semiconductor portion 4 atthe same potential as the source semiconductor portion 7 and thecapacitance between the p⁺ type buried semiconductor portion and thedrain semiconductor portion turns from the gate-drain capacitance to thesource-drain capacitance, so as to enable high-frequency operation.

(Thirteenth Embodiment) Next, the thirteenth embodiment, which is amodification of the first embodiment, will be described with referenceto FIG. 25. For a vertical JFET in the thirteenth embodiment,constitutive elements similar to those in the configuration of thevertical JFET 1 a described in the first embodiment are denoted by thesame reference symbols. The structure of the drift semiconductor portiondifferent from the first embodiment will be described below.

FIG. 25 is a sectional view of a vertical JFET 1 r in the thirteenthembodiment. The thirteenth embodiment is different in the structure ofthe drift semiconductor portion from the first embodiment. Namely, thefirst embodiment was directed to the configuration wherein the driftsemiconductor portion had the same conductivity type as the n⁺ typedrain semiconductor portion 2, whereas the thirteenth embodiment isdirected to a configuration wherein the drift semiconductor portion hasa Super Junction (SJ) structure composed of semiconductor regions ofdifferent conductivity types.

With reference to FIG. 25, the drift semiconductor portion is placed ona principal surface of the n⁺ type drain semiconductor portion 2. Thedrift semiconductor portion has p-type semiconductor regions 31, 33 andan n-type semiconductor region 32 extending along a reference planeintersecting with the principal surface of the n⁺ type drainsemiconductor portion 2. The p-type semiconductor regions 31, 33 arearranged so as to place the n-type semiconductor region 32 in between.Junctions between the p-type semiconductor regions and the n-typesemiconductor region are located between p⁺ type gate semiconductorportions 41, 42 and the n⁺ type drain semiconductor portion 2.

The p-type semiconductor regions 31, 33 are located between the p⁺ typegate semiconductor portions 41, 42 and the n⁺ type drain semiconductorportion 2 and extend along the p⁺ type gate semiconductor portions 41,42 (in the x-axis direction in the drawing).

The n-type semiconductor region 32 is located between the n⁺ type drainsemiconductor portion 2 and the n-type channel semiconductor portion 5existing between the p⁺ type gate semiconductor portion 41 and the p⁺type gate semiconductor portion 42 and extends along the p⁺ type gatesemiconductor portions 41, 42 (in the x-axis direction in the drawing).The n-type semiconductor region 32 has the same conductivity type as theconductivity type of the drain semiconductor portion 2.

FIG. 26 is a sectional view of a vertical JFET 1 s showing another formhaving the super junction structure. The super junction structure isalso applicable to the drift semiconductor portion of the vertical JFET1 f described in the seventh embodiment, as shown in FIG. 26. FIG. 27 isa sectional view of a vertical JFET 1 t showing still another formhaving the super junction structure. As shown in FIG. 27, the superjunction structure is also applicable to the drift semiconductor portionof the vertical JFET 1 g described in the ninth embodiment. The superjunction structure is also applicable to the vertical JFETs described inthe other embodiments.

In the vertical JFETs 1 r, 1 s, and 1 t in the present embodiment, thedrift semiconductor portion is comprised of a plurality of semiconductorregions of different conductivity types. When the drift semiconductorportion has the structure as described above, the whole of the driftsemiconductor portion is fully depleted at a high drain voltage. Thisresults in decreasing the maximum of the electric field in the driftsemiconductor portion. Therefore, the thickness of the driftsemiconductor portion can be decreased. For this reason, the on-stateresistance becomes lower.

The dopant concentration of the p-type semiconductor regions 31, 33 ispreferably approximately equal to that of the n-type semiconductorregion 32. In a preferred example where the breakdown voltage of 500 Vis assumed, the dopant concentrations of the p-type semiconductorregions 31, 33 and the n-type semiconductor region 32 are approximately2.7×10¹⁷ cm⁻³. In another preferred example where the breakdown voltageof 500 V is assumed, the widths (in the y-axis direction in the drawing)of the p-type semiconductor regions 31, 33 and the n-type semiconductorregion 32 are approximately 0.5 μm. In this structure the depletionlayer lengthens into the whole of the p-type semiconductor regions andinto the whole of the n-type semiconductor region. Since the depletionlayer lengthens into the both semiconductor regions in this manner, theconcentration of the electric field in the drift semiconductor portionis alleviated.

(Fourteenth Embodiment) The positional relation of the n-typesemiconductor region and p-type semiconductor regions with the gatesemiconductor portions is not limited to those described in theembodiments heretofore. FIG. 28A is a schematic diagram showing apositional relation between each of semiconductor regions and gatesemiconductor portions in the fourteenth embodiment. The p-typesemiconductor regions 31, 33 and the n-type semiconductor region 32 allextend in a predetermined axial direction (the x-axis direction in thedrawing). The p-type semiconductor regions 31, 33 are arranged so as toplace the n-type semiconductor region 32 in between. Junctions betweenthe p-type semiconductor regions and the n-type semiconductor region arelocated under the p⁺ type gate semiconductor portions 41, 42.

In contrast to it, FIG. 28B is a schematic diagram showing anotherpositional relation between each of semiconductor regions and gatesemiconductor portions in the fourteenth embodiment. P-typesemiconductor regions 31, 33 and n-type semiconductor regions 32, 34 allextend in a predetermined axial direction (the x-axis direction in thedrawing). The p-type semiconductor regions 31, 33 and the n-typesemiconductor regions 32, 34 are alternately arranged. Junctions betweenthe p-type semiconductor regions and the n-type semiconductor regionsare located, not only under the p⁺ type gate semiconductor portions 41,42, but also between the gate semiconductor portions.

FIG. 28C is a schematic diagram showing a positional relation betweeneach of semiconductor regions and gate semiconductor portions in stillanother form. P-type semiconductor regions 31, 33 and n-typesemiconductor region 32 all extend in a predetermined axial direction(the y-axis direction in the drawing). The p-type semiconductor regions31, 33 are arranged so as to place the n-type semiconductor region 32 inbetween. The n-type semiconductor region may consist of a plurality ofregions.

(Fifteenth Embodiment)The following will describe a method of formingn-type semiconductor regions and p-type semiconductor regionsconstituting the super junction structure, in a production method of avertical JFET having the super junction structure.

(n-Type Semiconductor Layer Forming Step) First, an n⁺ type SiCsemiconductor substrate is prepared. The n-type impurity concentrationof the substrate is as high as this substrate can be used as a drainsemiconductor portion. As shown in FIG. 29A, an SiC film 3 is grown onthe front surface of the n⁺ type drain semiconductor portion 2 byepitaxial growth. In a preferred example where the breakdown voltage of500 V is assumed, the thickness T8 of the SiC film 3 is not less than2.0 μm nor more than 3.0 μm. The conductivity type of the SiC film 3 isthe same as that of the drain semiconductor portion 2. The dopantconcentration of the SiC film 3 is lower than that of the n⁺ type drainsemiconductor portion 2. N-type semiconductor layers 32, 34, and 36 areformed from this SiC film 3.

(p-Type Semiconductor Layer Forming Step) A step of forming p-typesemiconductor layers will be described with reference to FIG. 29B. Usinga predetermined mask M, regions 31 a, 31 c, 31 e, and 31 g formed on then-type semiconductor layer 3 are selectively ion-implanted with a dopantA10 to form p-type semiconductor layers 311, 331, 351, and 371 having apredetermined depth. After the p-type semiconductor layers are formed,the mask M is removed.

(Drift Semiconductor Portion Forming Step) A step of forming a driftsemiconductor portion in a desired thickness will be described withreference to FIG. 29C. Namely, the n-type semiconductor layer formingstep and the p-type semiconductor layer forming step are alternatelyrepeated to form the drift semiconductor portion having the superjunction structure on the n⁺ type drain semiconductor portion 2. As aresult, the semiconductor layer 3 having a predetermined thickness (inthe z-axis direction in the drawing) is formed. The above described themethod of forming the drift semiconductor portion having the n-typesemiconductor regions and the p-type semiconductor regions. The othersteps are similar to those in the second, sixth, and eighth embodiments,but are not limited to these.

(Sixteenth Embodiment) FIG. 30 is a sectional view of a vertical JFET 1u in the sixteenth embodiment. As shown in FIG. 30, the vertical JFET 1u has an n⁺ type drain semiconductor portion 2, an n-type driftsemiconductor portion 3, a p-type buried semiconductor portion 4, ann-type channel semiconductor portion 5, a p⁺ type gate semiconductorportion 6, and an n⁺ type source semiconductor portion 7.

The vertical JFET 1 u has a vertical structure in which the majoritycarriers migrate in the direction from one surface toward the othersurface of this device (hereinafter referred to as a “currentdirection”). FIG. 30 shows a coordinate system. This coordinate systemis defined so that the current direction of the JFET channel portion isaligned with the y-axis.

The n⁺ type drain semiconductor portion 2 has a pair of opposedsurfaces. The n⁺ type drain semiconductor portion 2 can be a substratedoped with a dopant and, in a preferred example, this substrate is madeof SiC (silicon carbide). The dopant to be added to SiC can be one ofdonor impurities such as N (nitrogen), P (phosphorus), and As (arsenic)which are elements of Group 5 in the periodic table. The n⁺ type drainsemiconductor portion 2 has a drain electrode 2 a on one (back surface)of the pair of surfaces. The drain electrode 2 a is made of metal.

The n-type drift semiconductor portion 3 is placed on the other (frontsurface) of the pair of surfaces of the n⁺ type drain semiconductorportion 2. The n-type drift semiconductor portion 3 has first to fourthregions 3 a, 3 b, 3 c, and 3 d arranged in order in the y-axisdirection, on its front surface. The first to fourth regions 3 a, 3 b, 3c, and 3 d extend in a predetermined axial direction (the x-axisdirection in FIG. 30) and, in a preferred example, they are rectangular.The p-type buried semiconductor portion 4 is placed on the first,second, and fourth regions 3 a, 3 b, and 3 d. The channel semiconductorportion 5 is placed on the first to third regions 3 a, 3 b, and 3 c. Theconductivity type of the drift semiconductor portion 3 is the same asthat of the drain semiconductor portion 2, and the dopant concentrationof the drift semiconductor portion 3 is lower than the dopantconcentration of the drain semiconductor portion 2. In a preferredexample, the drift semiconductor portion 3 is made of SiC (siliconcarbide) doped with a dopant.

The p-type buried semiconductor portion 4 is placed on the first,second, and fourth regions 3 a, 3 b, and 3 d. The conductivity type ofthe buried semiconductor portion 4 is opposite to that of the driftsemiconductor portion 3. In a preferred example, the p-type buriedsemiconductor portion 4 is made of SiC (silicon carbide) doped with adopant. This dopant can be one of acceptor impurities such as B (boron)and Al (aluminum) which are elements of Group 3 in the periodic table.

The n-type channel semiconductor portion 5 is placed on the first tothird regions 3 a, 3 b, and 3 c. The n-type channel semiconductorportion 5 extends in a predetermined axial direction (the y-axisdirection in FIG. 30) along the p-type buried semiconductor portion 4.The n-type channel semiconductor portion 5 is electrically connected tothe n-type drift semiconductor portion 3 in the third region 3 c. Sincethe conductivity type of the channel semiconductor portion 5 is oppositeto that of the buried semiconductor portion 4, a pn junction is createdat the interface between the buried semiconductor portion 4 and thechannel semiconductor portion 5. The drain current flowing in the n-typechannel semiconductor portion 5 is controlled by the p-type buriedsemiconductor portion 4. The dopant concentration of the n-type channelsemiconductor portion 5 is lower than that of the n⁺ type drainsemiconductor portion 2. In a preferred example the n-type channelsemiconductor portion 5 is made of SiC doped with a dopant. In apreferred example the channel length (in the y-axis direction in thedrawing) is greater than ten times the channel thickness (in the z-axisdirection in the drawing).

The p⁺ type gate semiconductor portion 6 is placed on the p-type buriedsemiconductor portion 4 and fourth region 3 d. The p⁺ type gatesemiconductor portion 6 extends in the vertical direction (the x-axisdirection in FIG. 30). A gate electrode 6 a is placed on the frontsurface of the p⁺ type gate semiconductor portion 6. The gate electrode6 a is made of metal. The p⁺ type gate semiconductor portion 6 connectsthe p-type buried semiconductor portion 4 to the gate electrode 6 a.

The n⁺ type source semiconductor portion 7 is placed on the n-typechannel semiconductor portion 5 and first region 3 a. The sourcesemiconductor portion 7 has the same conductivity type as theconductivity type of the drain semiconductor portion 2. The sourcesemiconductor portion 7 is connected through the channel semiconductorportion 5 to the drift semiconductor portion 3. A source electrode 7 ais placed on the n⁺ type source semiconductor portion 7. The sourceelectrode 7 a is made of metal. The n-type channel semiconductor portion5 is isolated from the source electrode 7 a by insulating films 8, 9such as silicon oxide films.

(Seventeenth Embodiment) Next, a production method of the vertical JFET1 u will be described. FIGS. 31A to 31C, FIGS. 32A to 32C, FIGS. 33A to33C, FIGS. 34A to 34C, and FIG. 35 are sectional views showingproduction steps of the vertical JFET 1 u in the seventeenth embodiment.

(Drain Semiconductor Film Forming Step) First, a substrate is preparedas shown in FIG. 31A. An example of the substrate is an n⁺ type SiCsemiconductor substrate. The dopant concentration of the substrate is ashigh as the substrate can be used as the drain semiconductor portion 2.

(Drift Semiconductor Film Forming Step) As shown in FIG. 31B, an SiCfilm 3 is grown on the front surface of the n⁺ type drain semiconductorportion 2 by epitaxial growth. The thickness T1 of the SiC film 3 is,for example, 10 μm. The conductivity type of the SiC film 3 is the sameas that of the n⁺ type drain semiconductor portion 2. The dopantconcentration of the SiC film 3 is lower than that of the n⁺ type drainsemiconductor portion 2. The dopant concentration of the SiC film 3 is,for example, approximately 1×10¹⁶/cm³. The n-type drift semiconductorportion is formed from this SiC film 3.

(Buried Semiconductor Portion Forming Step) A step of forming a buriedsemiconductor portion will be described with reference to FIG. 31C. Amask M1 having a pattern extending in a predetermined axial direction(the x-axis direction in the drawing) is formed. Using this mask M1, aregion 3 e formed on the SiC film 3 is selectively ion-implanted with adopant A1 to form a p-type buried semiconductor portion 4 having apredetermined depth. The depth D1 of the p-type buried semiconductorportion 4 is, for example, about 1.2 μm. The dopant concentration of thep-type buried semiconductor portion 4 is, for example, about 1×10¹⁸/cm³.After the buried semiconductor portion is formed, the mask M1 isremoved.

(Channel Semiconductor Film Forming Step) As shown in FIG. 32A, an SiCfilm 5 is grown on the front surface of the p-type buried semiconductorportion 4 and on the SiC film 3 by epitaxial growth. The thickness T2 ofthe SiC film 5 is, for example, approximately 0.3 μm. The conductivitytype of the SiC film 5 is the same as that of the n⁺ type drainsemiconductor portion 2. The dopant concentration of the SiC film 5 islower than the dopant concentration of the n⁺ type drain semiconductorportion 2. The dopant concentration of the SiC film 5 is, for example,approximately 1×10¹⁷/cm³. The n-type channel semiconductor portion isformed from this SiC film 5. In the present embodiment a single SiC filmwas formed for each of the n-type drift semiconductor portion and then-type channel semiconductor portion, but the production method mayinclude a plurality of film forming steps of repeatedly forming SiCfilms for each of the drift semiconductor portion and the channelsemiconductor portion. It is also possible to adopt a desired dopantconcentration profile for the SiC film, so as to make the SiC film 3serve as the drift semiconductor portion and the channel semiconductorportion.

(Source Semiconductor Film Forming Step) As shown in FIG. 32B, an SiCfilm 7 for n⁺ type source layer is grown on the front surface of the SiCfilm 5 by epitaxial growth. The thickness T3 of the SiC film 7 is, forexample, approximately 0.2 μm. The conductivity type of the SiC film 7is the same as that of the n⁺ type drain semiconductor portion 2. Thedopant concentration of the SiC film 7 is higher than the dopantconcentration of the SiC film 5. A mask M2 having a pattern extending ina predetermined axial direction (the x-axis direction in the drawing) isformed.

(Source and Channel Semiconductor Portion Forming Step) A step offorming a source semiconductor portion will be described with referenceto FIG. 32C. Using the mask M2, the n⁺ type source layer 7, and the SiCfilm 5 and SiC film 3 are selectively etched up to a depth D2. As aresult, the part of the n⁺ type source layer 7 and SiC film 5 covered bythe mask M2 remains unetched, so as to form an n⁺ type sourcesemiconductor portion. The thickness T4 of the SiC film 5 on the frontsurface of the p-type buried semiconductor portion in the regions notcovered by the mask largely affects the characteristics of JFET(intrinsic channel semiconductor portion). The etching depth D2 is, forexample, approximately 0.4 μm, and the thickness T4 of the etched SiCfilm 5 is, for example, approximately 0.1 μm. After the sourcesemiconductor portion is formed, the mask M2 is removed. A mask M3having a pattern extending in a predetermined axial direction (thex-axis direction in the drawing) is formed.

(p⁺ Type Semiconductor Portion Forming Step) A step of forming a p⁺ typegate semiconductor portion will be described with reference to FIG. 32C.Using the mask M3, a region 5 a formed on the SiC film 5 is selectivelyion-implanted with a dopant A2 to form a p⁺ type gate semiconductorportion 6. With reference to FIG. 33A, the p⁺ type gate semiconductorportion 6 reaching the p-type buried semiconductor portion 4 is formedin the semiconductor portion 5. After the p⁺ type semiconductor portionis formed, the mask M3 is removed.

(Thermal Oxidation Step) A step of thermally oxidizing the vertical JFET1 u will be described with reference to FIG. 33B. The vertical JFET 1 uis subjected to a thermal oxidation treatment. The thermal oxidationtreatment is a treatment of exposing SiC to an oxidizing atmosphere at ahigh temperature (e.g., about 1200° C.), to bring about chemicalreaction of silicon in each semiconductor portion with oxygen to form asilicon oxide film (SiO₂). As a result, the front surface of eachsemiconductor portion is covered by an oxide film 8.

(Aperture Forming Step) A step of forming apertures for formation ofgate electrodes will be described with reference to FIG. 33C. Using amask of a photoresist, the oxide film 8 is selectively etched to formapertures. Front surface parts of the p⁺ type gate semiconductor portion6 and the n⁺ type source semiconductor portion 7 are exposed in therespective apertures. The exposed portions become conducting portionsone to the gate electrode and the other to the source electrode. Afterthe apertures are formed, the resist mask is removed.

(Electrode Forming Step) A step of forming electrodes will be describedwith reference to FIG. 34A. A metal film for electrodes, for example, Niis deposited on the front surface of the vertical JFET 1 u. Next, a maskof a photoresist having a predetermined shape is formed. Using thismask, the metal film for electrodes is selectively etched. As a result,the part of the metal film for electrodes covered by the resist patternremains unetched, to form a gate electrode 6 a and a source ohmicelectrode 7 a. After the electrodes are formed, the resist mask isremoved.

It is also possible to adopt a method of directly depositing the metalfilm for the electrode material including the area on the photoresist,without removing the photoresist pattern in the aperture forming step,and thereafter removing the metal film on the photoresist simultaneouslywith the removal of the photoresist. After the electrodes are formed onthe front surface, the entire front surface is covered by a resist, ametal film for an electrode material is deposited over the entire frontsurface, and the resist on the front surface is removed. Then a thermaltreatment is carried out in an inert gas atmosphere such as argon at ahigh temperature (e.g., 1050° C.), thereby forming ohmic connectionsbetween each electrode (source, drain, or gate) and each semiconductorportion.

(Insulating Film Forming Step) A step of forming an insulating film willbe described with reference to FIG. 34B. An insulating film 9 of SiO₂ orSiON is formed over the entire front surface of the vertical JFET 1 u byCVD (Chemical Vapor Deposition) or the like.

(Aperture Forming Step) A step of forming an aperture for formation ofthe source electrode will be described with reference to FIG. 34C. Usinga mask of a photoresist, the oxide film 8 and insulating film 9 areselectively etched to form a contact hole 9 a. The front surface part ofthe source ohmic electrode 7 a is exposed in the aperture. The exposedportion becomes a conducting part to the source electrode. The contacthole 9 a is formed so as to reach the source ohmic electrode 7 a. Afterthe contact hole 9 a is formed, the resist mask is removed.

(Electrode Forming Step) Next, a step of forming a source electrode willbe described with reference to FIG. 35. The source electrode 7 b isformed so as to be in contact with the front surface of the sourcesemiconductor portion 7. The source electrode 7 b is in contact with thesource semiconductor portion 7 through the contact hole 9 a shown inFIG. 34C. The material of the wiring metal film can be suitably selectedfrom aluminum (Al) and Al alloys in terms of low resistance, easiness ofmicroprocessing, and adhesion, but may be copper (Cu) or tungsten (W).However, the material is not limited to these.

The vertical JFET 1 u in the sixteenth embodiment is completed throughthe steps described above. In the structure of the vertical JFET 1 u,the p-type buried semiconductor portion 4 and the n-type channelsemiconductor portion 5 can be arranged on the n-type driftsemiconductor portion 3. Therefore, a desired drain blocking voltage canbe acquired by the thickness of the n-type drift semiconductor portion3, without increasing the chip size. Consequently, the breakdown voltagebetween the source and the drain can be improved. Carriers flow not onlyunder the n-type channel semiconductor portion 5, but also in the n-typedrift semiconductor portion 3 located under the p-type buriedsemiconductor portion 4. Accordingly, the on-state resistance can belowered while maintaining the breakdown voltage. Namely, the presentstructure is suitable for high-breakdown-voltage JFETs.

In the present embodiment the semiconductor portions of the drain,source, and gate are made of SiC. SiC is superior in the followingrespects to such semiconductors as Si (silicon) and GaAs (galliumarsenide). Namely, since SiC has a high melting point and a largebandgap (forbidden band width), it facilitates operation at hightemperatures of the device. Since SiC has a large breakdown electricfield, it enables achievement of high breakdown voltage and low loss.Furthermore, it has high thermal conductivity and thus presents theadvantage of facilitating heat liberation.

(Eighteenth Embodiment) Next, the eighteenth embodiment, which is amodification of the sixteenth embodiment, will be described withreference to FIG. 36. For a vertical JFET in the eighteenth embodiment,constitutive elements similar to those in the configuration of thevertical JFET 1 u described in the sixteenth embodiment are denoted bythe same reference symbols. A configuration of the channel semiconductorportion different from the sixteenth embodiment will be described below.

FIG. 36 is a sectional view of a vertical JFET 1 v in the eighteenthembodiment. The eighteenth embodiment is different in the structure ofthe channel region from the sixteenth embodiment. Specifically, thesixteenth embodiment was directed to the configuration wherein then-type channel semiconductor portion 5 was in contact with the n⁺ typesource semiconductor portion 7 above the first region 3 a, whereas theeighteenth embodiment is directed to a configuration wherein thevertical JFET 1 v further has an n⁻ type semiconductor portion 10between the n-type channel semiconductor portion 5 and the n⁺ typesource semiconductor portion 7. In this structure the n-type channelsemiconductor portion 5 is not subjected to etching, so that thethickness of the channel semiconductor portion is not affected byvariations due to the etching step. Therefore, it is feasible todecrease the individual differences in electrical characteristics amongvertical JFETs 1 v.

The n⁻ type semiconductor portion 10 is placed on the n-type channelsemiconductor portion 5 and the first to third regions 3 a, 3 b, and 3c. The conductivity type of the semiconductor portion 10 is the same asthat of the channel semiconductor portion 5. The dopant concentration ofthe n⁻ type semiconductor portion 10 is lower than that of the n-typechannel semiconductor portion 5. The dopant concentration of the n⁻ typesemiconductor portion 10 is, for example, approximately 1×10¹⁶/cm³. In apreferred example, the n⁻ type semiconductor portion 10 is made of SiC(silicon carbide) doped with a dopant.

The channel structure consisting of the n-type semiconductor portion andthe n⁻ type semiconductor portion described in the present embodiment isapplicable not only to the sixteenth embodiment, but also to all theembodiments described hereinafter (the twentieth to twenty eighthembodiments).

(Nineteenth Embodiment) Next, the nineteenth embodiment, which is amodification of the seventeenth embodiment, will be described withreference to FIGS. 37A to 37C. For a production method of a verticalJFET in the nineteenth embodiment, constitutive elements similar tothose in the production method of the vertical JFET 1 u described in theseventeenth embodiment are denoted by the same reference symbols. Thefollowing will describe a channel semiconductor film forming step, an n⁻type semiconductor film forming step, and a source semiconductor portionforming step different from the seventeenth embodiment.

(Channel Semiconductor Film Forming Step) The channel semiconductor filmforming step is carried out in succession to the gate semiconductorportion forming step. As shown in FIG. 37A, an SiC film 5 is grown onthe front surface of the p⁺ type gate semiconductor portion 4 and on theSiC film 3 by epitaxial growth. The thickness T6 of the SiC film 5 is,for example, approximately 0.1 μm. The conductivity type of the SiC film5 is the same as that of the n⁺ type drain semiconductor portion 2. Thedopant concentration of the SiC film 5 is lower than that of the n⁺ typedrain semiconductor portion 2. The dopant concentration of the SiC film5 is, for example, approximately 1×10¹⁷/cm³ The n-type channelsemiconductor portion is formed from this SiC film 5.

(n⁻ Type Semiconductor Film Forming Step) As shown in FIG. 37B, an SiCfilm 10 is grown on the front surface of the SiC film 5 by epitaxialgrowth. The thickness T7 of the SiC film 10 is, for example,approximately 0.2 μm. The conductivity type of the SiC film 10 is thesame as that of the SiC film 5. The dopant concentration of the SiC film10 is lower than that of the SiC film 5. The dopant concentration of theSiC film 10 is, for example, approximately 1×10¹⁶/cm³. The n⁻ typesemiconductor portion is formed from this SiC film 10.

(Source Semiconductor Film Forming Step) Subsequently, a step of forminga source semiconductor film will be described with reference to FIG.37B. An SiC film 7 for n⁺ type source layer is formed on the frontsurface of the SiC film 10 by epitaxial growth. The thickness of the SiCfilm 7 is, for example, approximately 0.2 μm. The conductivity type ofthe SiC film 7 is the same as that of the n⁺ type drain semiconductorportion 2. The dopant concentration of the SiC film 7 is higher thanthat of the SiC film 10 and is, for example, approximately 1×10¹⁹/cm³.

(Source Semiconductor Portion Forming Step) A step of forming a sourcesemiconductor portion will be described with reference to FIG. 37C. Amask M4 having a pattern covering a predetermined region is formed.Using the mask M4, the n⁺ type source layer 7 and the n⁻ typesemiconductor layer 10 are selectively etched. As a result, the n⁺ typesource layer 7 and n⁻ type semiconductor layer 10 covered by the resistpattern remain unetched in part, so as to become an n⁺ type sourcesemiconductor portion. The etching depth D3 is so deep as not to reachthe semiconductor layer 5. After the source semiconductor portion isformed, the mask M4 is removed.

The above described the channel semiconductor film forming step, n⁻ typesemiconductor film forming step, and source semiconductor portionforming step different from the seventeenth embodiment. The p⁺ typesemiconductor portion forming step is carried out in succession to thesource semiconductor portion forming step. The other steps are similarto those in the seventeenth embodiment. According to the productionmethod of the vertical JFET in the present embodiment, the SiC film 5 isnot etched in the source semiconductor portion forming step. Therefore,the thickness of the channel semiconductor portion is not affected byvariations due to the etching step. Therefore, it is feasible todecrease individual differences in electrical characteristics amongtransistors.

(Twentieth Embodiment)A vertical JFET 1 w in the twentieth embodimentwill be described. FIG. 38 is a perspective view of the vertical JFET 1w. As shown in FIG. 38, the vertical JFET 1 w has an n⁺ type drainsemiconductor portion 2, an n-type drift semiconductor portion 3, p⁺type gate diffused semiconductor portions 41, 42, 43, 44, and 45, ann-type channel semiconductor portion 5, and an n⁺ type sourcesemiconductor portion 7 having a mass source electrode 7 a on its frontsurface.

The p⁺ type gate diffused semiconductor portions 41 to 45 function asgate wiring for external connections provided in the peripheral part ofa primitive cell or a semiconductor chip of transistors and as a gatefor controlling the channel width. Namely, the p⁺ type gate diffusedsemiconductor portions 41 to 45 are formed as buried inside the n-typechannel semiconductor portion 5, at predetermined intervals in they-axis direction. Each of the p⁺ type gate diffused semiconductorportions 41 to 45 extends in a predetermined axial direction (the x-axisdirection in FIG. 38). In a preferred example, the p⁺ type gate diffusedsemiconductor portions 41 to 45 are made of SiC (silicon carbide) dopedwith a dopant. A gate electrode 4 a is placed so as to surround the masssource electrode 7 a described hereinafter.

The n⁺ type source semiconductor portion 7 is placed on the n-typechannel semiconductor portion 5. The source semiconductor portion 7 hasthe same conductivity type as the conductivity type of the drainsemiconductor portion 2. The n⁺ type source semiconductor portion 7 isconnected through the n-type channel semiconductor portion 5 to then-type drift semiconductor portion 3. The mass source electrode 7 a isplaced on the front surface of the n⁺ type source semiconductor portion7. The mass source electrode 7 a is made of metal. The p⁺ type gatediffused semiconductor portion 41 and n⁺ type source semiconductorportion 7 are electrically connected by the mass source electrode 7 a.

The structure of the vertical JFET 1 w in the present embodimentobviates the need for gate wiring on the front surface because the gatewiring is buried inside the semiconductor. Therefore, the wiring on thefront surface of a chip is simplified from the viewpoint of the entiresemiconductor chip comprised of a plurality of transistors. It is alsofeasible to decrease the surface area of the chip.

(Twenty First Embodiment) Next, the twenty first embodiment, which is amodification of the sixteenth embodiment, will be described withreference to FIG. 39. For a vertical JFET in the twenty firstembodiment, constitutive elements similar to those in the configurationof the vertical JFET 1 u described in the sixteenth embodiment aredenoted by the same reference symbols. Differences from the sixteenthembodiment will be described below.

FIG. 39 is a sectional view of a vertical JFET 1 x in the twenty firstembodiment. The twenty first embodiment is different in the structure ofthe gate semiconductor portion from the sixteenth embodiment. Namely,the twenty first embodiment is directed to a configuration wherein a p⁺type gate semiconductor portion 11 is placed on the n-type channelsemiconductor portion 5 and the second and third regions 3 b, 3 c.

The conductivity type of the gate semiconductor portion 11 is oppositeto that of the channel semiconductor portion 5. The p-type dopantconcentration of the gate semiconductor portion 11 is higher than then-type dopant concentration of the channel semiconductor portion 5, sothat the depletion layer lengthens in the channel semiconductor portion.The dopant concentration of the p⁺ type gate semiconductor portion 11is, for example, approximately 1×10¹⁸/cm³. In a preferred example, thep-type gate semiconductor portion 11 is made of SiC doped with a dopant.The thickness of the p-type gate semiconductor portion is, for example,approximately 0.3 μm. Since the vertical JFET 1 x has the n-type channelsemiconductor portion 5 between the p-type buried semiconductor portion4 and the p-type gate semiconductor portion 11, the channel can becontrolled from both sides of the n-type channel semiconductor portion5. This structure increases the controllable channel width, incomparison with a case where the channel is controlled from one side ofthe n-type channel semiconductor portion 5. This substantializes thestructure for easy implementation of the normally-off transistor.

(Twenty Second Embodiment) Next, the twenty second embodiment, which isa modification of the seventeenth embodiment, will be described withreference to FIGS. 40A and 40B. For a production method of a verticalJFET in the twenty second embodiment, constitutive elements similar tothose in the production method of the vertical JFET 1 u described in theseventeenth embodiment are denoted by the same reference symbols. Thefollowing will describe a p⁺ type gate semiconductor portion formingstep different from the seventeenth embodiment.

(p⁺ Type Gate Semiconductor Portion Forming Step) The p⁺ type gatesemiconductor portion forming step is carried out in succession to thep⁺ type semiconductor portion forming step. A step of forming a p⁺ typegate semiconductor portion will be described with reference to FIG. 40A.Using a mask M3 having a predetermined shape, a region 5 a on the SiCfilm 5 is selectively ion-implanted with a dopant A2 to form a p⁺ typegate semiconductor portion 11 having a predetermined depth. The depth D4of the channel layer defined through the formation of the p⁺ type gatesemiconductor portion 11 is determined according to the threshold of thevertical JFET. For example, D4 is approximately 0.2 μm. After the gatesemiconductor portion is formed, the mask M3 is removed. As a result,the vertical JFET as shown in FIG. 40B is obtained. The above describedthe p⁺ type gate semiconductor portion forming step different from theseventeenth embodiment. A thermal oxidation step is carried out insuccession to the p⁺ type gate semiconductor portion forming step. Theother steps are similar to those in the seventeenth embodiment, but arenot limited to it.

(Twenty Third Embodiment) The twenty third embodiment, which is amodification of the twenty first embodiment, will be described withreference to FIG. 41. For a vertical JFET in the twenty thirdembodiment, constitutive elements similar to those in the configurationof the vertical JFET 1 x described in the twenty first embodiment aredenoted by the same reference symbols. The following will describe thestructure of the gate semiconductor portion different from the twentyfirst embodiment.

FIG. 41 is a sectional view of a vertical JFET 1 y in the twenty thirdembodiment. The twenty third embodiment is different in the structure ofthe gate semiconductor portion from the twenty first embodiment. Namely,the twenty third embodiment is directed to a configuration wherein thevertical JFET 1 y has a p⁺ type gate semiconductor portion 12. The pnjunction between the n-type channel semiconductor portion 5 and the p⁺type gate semiconductor portion 12 is a heterojunction. The n-typechannel semiconductor portion 5 is made of SiC. The p⁺ type gatesemiconductor portion 12 is made of polysilicon. This obviates the needfor the epitaxial growth step of SiC for formation of the p⁺ type gatesemiconductor portion 11 described in the twenty first embodiment, andthus enables easy construction of the vertical JFET 1 y.

(Twenty Fourth Embodiment) Next, the twenty fourth embodiment, which isa modification of the twenty first embodiment, will be described withreference to FIGS. 42A and 42B. For a vertical JFET in the twenty fourthembodiment, constitutive elements similar to those in the configurationof the vertical JFET 1 x described in the twenty first embodiment aredenoted by the same reference symbols. Differences from the twenty firstembodiment will be described below.

FIG. 42A is a sectional view of a vertical JFET 1 z in the twenty fourthembodiment. The twenty fourth embodiment is different in the structureof the gate semiconductor portion from the twenty first embodiment.Namely, the twenty fourth embodiment is directed to a configurationwherein the channel region is located between the p⁺ type gatesemiconductor portion 4 and the p⁺ type gate semiconductor portion 11.The vertical JFET 1 z further has p⁺ type semiconductor portions 13placed in the channel region of the n-type channel semiconductor portion5. The p⁺ type semiconductor portions 13 are placed on a region 4 a ofthe p⁺ type gate semiconductor portion 4. The p⁺ type semiconductorportions 13 are placed so as to partially penetrate the n-type channelsemiconductor portion 5.

FIG. 42B is a sectional view along III-III line of the vertical JFET 1z. As shown in FIG. 42B, the p⁺ type semiconductor portions 13 arearranged at predetermined intervals in the x-axis direction inside then-type channel semiconductor portion 5. The dopant concentration of thep⁺ type semiconductor portions 13 is higher than that of the n-typechannel semiconductor portion 5. For this reason, the depletion layerlengthens mainly in the n-type channel semiconductor portion 5. In apreferred example, the p⁺ type semiconductor portions 13 are made of SiCdoped with a dopant. In the vertical JFET 1 z, the p⁺ type gatesemiconductor portion 4 is electrically connected through the p⁺ typesemiconductor portions 13 to the p⁺ type gate semiconductor portion 11.This keeps the p⁺ type gate semiconductor portion 4 at the samepotential as the p⁺ type gate semiconductor portion 11, and it is thusfeasible to increase the thickness of the channel layer.

(Twenty Fifth Embodiment) Next, the twenty fifth embodiment, which is amodification of the sixteenth embodiment, will be described withreference to FIGS. 43A and 43B. For a vertical JFET in the twenty fifthembodiment, constitutive elements similar to those in the configurationof the vertical JFET 1 u described in the sixteenth embodiment aredenoted by the same reference symbols. Differences from the sixteenthembodiment will be described below.

FIG. 43A is a sectional view of a vertical JFET 10 a in the twenty fifthembodiment. The twenty fifth embodiment is different in the structure ofthe channel semiconductor portion from the sixteenth embodiment. Namely,the twenty fifth embodiment is directed to a configuration wherein thechannel semiconductor portion has the pulse-doped structure.

As shown in FIG. 43B, the pulse-doped semiconductor portion 14 iscomprised of an alternate stack of n⁻ type SiC layers 141 to 144 and n⁺type SiC layers 145 to 147. The dopant concentration of the n⁻ type SiClayers 141 to 144 is lower than that of the n⁺ type SiC layers 145 to147. The dopant concentration of the n⁻ type SiC layers 141 to 144 is,for example, approximately 1×10¹⁶/cm³. The thickness T8 of the n⁻ typeSiC layers 141 to 144 is, for example, about 10 nm. The dopantconcentration of the n⁺ type SiC layers 145 to 147 is 1×10¹⁷/cm³ to1×10¹⁸/cm³. The thickness T9 of the n⁺ type SiC layers 145 to 147 is,for example, about 10 nm. In such structure, carriers migrate in thelow-concentration layers with larger carrier mobility than in thehigh-concentration layers, so as to increase the electric currentflowing in the channel region. As a result, the on-state resistance canbe reduced.

(Twenty Sixth Embodiment) Next, the twenty sixth embodiment, which is amodification of the sixteenth embodiment, will be described withreference to FIG. 44. For a vertical JFET in the twenty sixthembodiment, constitutive elements similar to those in the configurationof the vertical JFET 1 u described in the sixteenth embodiment aredenoted by the same reference symbols. The following will describe thestructure of the drift semiconductor portion different from thesixteenth embodiment.

FIG. 44 is a sectional view of a vertical JFET 10 b in the twenty sixthembodiment. The twenty sixth embodiment is different in the structure ofthe drift semiconductor portion from the sixteenth embodiment.Specifically, the sixteenth embodiment was directed to the configurationwherein the drift semiconductor portion had the same conductivity typeas the conductivity type of the n⁺ type drain semiconductor portion 2,whereas the twenty sixth embodiment is directed to a configurationwherein the drift semiconductor portion has the Super Junction (SJ)structure composed of semiconductor regions of different conductivitytypes.

With reference to FIG. 44, the drift semiconductor portion is placed onthe principal surface of the n⁺ type drain semiconductor portion 2. Thedrift semiconductor portion has p-type semiconductor regions 31, 33 andan n-type semiconductor region 32 extending along a reference planeintersecting with the principal surface of the n⁺ type drainsemiconductor portion 2. The p-type semiconductor regions 31, 33 arearranged so as to place the n-type semiconductor region 32 in between.Junction surfaces between the p-type semiconductor regions and then-type semiconductor region are located between the p⁺ type gatesemiconductor portions 41, 42 and the n⁺ type drain semiconductorportion 2.

The p-type semiconductor regions 31, 33 are located between the p⁺ typegate semiconductor portions 41, 42 and the n⁺ type drain semiconductorportion 2 and extend along the p⁺ type gate semiconductor portions 41,42 (in the x-axis direction in FIG. 44).

The n-type semiconductor region 32 is located between the n⁺ type drainsemiconductor portion 2 and the n-type channel semiconductor portion 5existing between the p⁺ type gate semiconductor portion 41 and the p⁺type gate semiconductor portion 42, and extends in the direction alongthe p⁺ type gate semiconductor portions 41, 42 (the x-axis direction inFIG. 44). The n-type semiconductor region 32 has the same conductivitytype as the conductivity type of the drain semiconductor portion 2.

The super junction structure is also applicable to the driftsemiconductor portion of the vertical JFET 1 x described in the twentyfirst embodiment, as shown in FIG. 45. The super junction structure isalso applicable to the drift semiconductor portion of the vertical JFET1 z described in the twenty fourth embodiment, as shown in FIG. 46. Thesuper junction structure is also applicable to the vertical JFETsdescribed in the other embodiments.

In the vertical JFET 10 b in the present embodiment, the driftsemiconductor portion is comprised of a plurality of semiconductorregions of different conductivity types. In the case of the driftsemiconductor portion having such structure, the whole of the driftsemiconductor portion is fully depleted with application of a high drainvoltage. Therefore, the maximum of the electric field in the driftsemiconductor portion becomes lower. Consequently, the thickness of thedrift semiconductor portion can be decreased. For this reason, theon-state resistance becomes smaller.

The dopant concentration of the p-type semiconductor regions 31, 33 ispreferably nearly equal to that of the n-type semiconductor region 32.In a preferred example where the breakdown voltage of 500 V is assumed,the dopant concentrations of the p-type semiconductor regions 31, 33 andthe n-type semiconductor region 32 are approximately 2.7×10¹⁷ cm⁻³. In apreferred example where the breakdown voltage of 500 V is assumed, thewidths (in the y-axis direction in the drawing) of the p-typesemiconductor regions 31, 33 and the n-type semiconductor region 32 areapproximately 0.5 μm. This permits the depletion layer to extend intothe entire p-type semiconductor regions and to extend into the entiren-type semiconductor region. Since the depletion layer extends into theboth semiconductor regions in this manner, the concentration of theelectric field in the drift semiconductor portion is alleviated.

(Twenty Seventh Embodiment) The positional relation of the gatesemiconductor portions with the n-type semiconductor region and thep-type semiconductor regions is not limited to those described in theembodiments heretofore. FIG. 47A is a schematic diagram showing apositional relation between each of semiconductor regions and the gatesemiconductor portions in the twenty seventh embodiment. The p-typesemiconductor regions 31, 33 and the n-type semiconductor region 32 allextend in a predetermined axial direction (the x-axis direction in thedrawing) The p-type semiconductor regions 31, 33 are arranged to placethe n-type semiconductor region 32 in between. Junctions between thep-type semiconductor regions and the n-type semiconductor region arelocated below the p⁺ type gate semiconductor portions 41, 42.

In contrast to it, FIG. 47B is a schematic diagram showing anotherpositional relation between each of semiconductor regions and the gatesemiconductor portions in the twenty seventh embodiment. The p-typesemiconductor regions 31, 33 and n-type semiconductor regions 32, 34 allextend in a predetermined axial direction (the x-axis direction in thedrawing). The p-type semiconductor regions 31, 33 and n-typesemiconductor regions 32, 34 are alternately arranged. Junctions betweenthe p-type semiconductor regions and the n-type semiconductor regionsare located not only under the p⁺ type gate semiconductor portions 41,42, but also between the gate semiconductor portions.

FIG. 47C is a schematic plan view showing a positional relation betweeneach of semiconductor regions and the gate semiconductor portions instill another form. The p-type semiconductor regions 31, 33 and n-typesemiconductor region 32 all extend in a predetermined axial direction(the y-axis direction in the drawing). The p-type semiconductor regions31, 33 are arranged so as to place the n-type semiconductor region 32 inbetween. The n-type semiconductor region may consist of a plurality ofregions.

(Twenty Eighth Embodiment) The following will describe a method offorming n-type semiconductor regions and p-type semiconductor regionsconstituting the super junction structure, in a production method of avertical JFET having the super junction structure.

(n-Type Semiconductor Layer Forming Step) First, an n⁺ type SiCsemiconductor substrate is prepared. The n-type impurity concentrationof the substrate is as high as this substrate can be used as a drainsemiconductor portion. As shown in FIG. 48A, an SiC film 3 is grown onthe front surface of the n⁺ type drain semiconductor portion 2 byepitaxial growth. In a preferred example where the breakdown voltage of500 V is assumed, the thickness T10 of the SiC film 3 is not less than2.0 μm nor more than 3.0 μm. The conductivity type of the SiC film 3 isthe same as that of the drain semiconductor portion 2. The dopantconcentration of the SiC film 3 is lower than that of the n⁺ type drainsemiconductor portion 2. N-type semiconductor layers 32, 34, and 36 areformed from this SiC film 3.

(p-Type Semiconductor Layer Forming Step) A step of forming p-typesemiconductor layers will be described with reference to FIG. 48B. Usinga predetermined mask M, regions 31 a, 31 c, 31 e, and 31 g formed on then-type semiconductor layer 3 are selectively ion-implanted with a dopantA3 to form p-type semiconductor layers 311, 331, 351, and 371 having apredetermined depth. After the p-type semiconductor layers are formed,the mask M is removed.

(Drift Semiconductor Portion Forming Step) A step of forming a driftsemiconductor portion having a desired thickness will be described withreference to FIG. 48C. Specifically, the n-type semiconductor layerforming step and the p-type semiconductor layer forming step arealternately repeated to form the drift semiconductor portion having thesuper junction structure on the n⁺ type drain semiconductor portion 2.As a result, the semiconductor layer 3 having a predetermined thickness(in the z-axis direction in the drawing) is formed. The above describedthe method of forming the drift semiconductor portion having the n-typesemiconductor regions and the p-type semiconductor regions. The othersteps are similar to those in the eighteenth, twelfth, and twenty secondembodiments, but are not limited to these.

The vertical JFETs and production methods thereof according to thepresent invention are not limited to the forms described in the aboverespective embodiments, but can be modified in various modificationforms according to other conditions or the like. For example, each ofthe above embodiments described the example in which the channel regionwas formed from the n-type semiconductor containing the donor impurity,but the present invention is also applicable to JFETs in which thechannel region is formed from a p-type semiconductor. In this case,however, the current direction and the polarities of the gate voltageapplied are reverse.

INDUSTRIAL APPLICABILITY

The present invention successfully provides the vertical junction fieldeffect transistors with low loss while maintaining a high drain blockingvoltage, and the production methods of the vertical junction fieldeffect transistors.

1. A vertical junction field effect transistor comprising: a drainsemiconductor portion; a drift semiconductor portion placed on aprincipal surface of the drain semiconductor portion and having first,second, third, and fourth regions extending in a predetermined axialdirection intersecting with the principal surface; a buriedsemiconductor portion having a conductivity type opposite to aconductivity type of the drift semiconductor portion and placed on thefirst, second, and third regions of the drift semiconductor portion; achannel semiconductor portion placed along the buried semiconductorportion, having the conductivity type opposite to the conductivity typeof the buried semiconductor portion, and electrically connected to thefourth region of the drift semiconductor portion; a source semiconductorportion placed on the channel semiconductor portion and the first regionof the drift semiconductor portion; and a gate semiconductor portionhaving a conductivity type opposite to a conductivity type of the drainsemiconductor portion and placed on the channel semiconductor portionand the third and fourth regions; wherein the gate semiconductor portionhas a plurality of projections extending in a direction from the thirdregion toward the fourth region, the channel semiconductor portion isplaced between the projections, and the projections are connected to theburied semiconductor portion.
 2. A vertical junction field effecttransistor comprising: a drain semiconductor portion; a driftsemiconductor portion placed on a principal surface of the drainsemiconductor portion and having first, second, third, and fourthregions extending in a predetermined axial direction intersecting withthe principal surface; a buried semiconductor portion having aconductivity type opposite to a conductivity type of the driftsemiconductor portion and placed on the first, second, and third regionsof the drift semiconductor portion; a channel semiconductor portionplaced along the buried semiconductor portion, having the conductivitytype opposite to the conductivity type of the buried semiconductorportion, and electrically connected to the fourth region of the driftsemiconductor portion; a source semiconductor portion placed on thechannel semiconductor portion and the first region of the driftsemiconductor portion; and a plurality of gate semiconductor portionshaving a conductivity type opposite to a conductivity type of the drainsemiconductor portion and placed on the channel semiconductor portionand the third and fourth regions; wherein each of the gate semiconductorportions extends in a direction from the third region toward the fourthregion, the channel semiconductor portion is placed between the gatesemiconductor portions, and each gate semiconductor portion is connectedto the buried semiconductor portion.
 3. A vertical junction field effecttransistor comprising: a drain semiconductor portion; a driftsemiconductor portion placed on a principal surface of the drainsemiconductor portion and having first, second, third, and fourthregions extending in a predetermined axial direction intersecting withthe principal surface; a buried semiconductor portion placed on aprincipal surface of the drift semiconductor portion and placed on thefirst, second, and third regions extending in the predetermined axialdirection intersecting with the principal surface; a channelsemiconductor portion placed along the buried semiconductor portion,having a conductivity type opposite to a conductivity type of the buriedsemiconductor portion, and electrically connected to the fourth regionof the drift semiconductor portion; and a gate semiconductor portionhaving a conductivity type opposite to a conductivity type of the driftsemiconductor portion and placed on the channel semiconductor portionand the third and fourth regions; wherein the gate semiconductor portionhas a plurality of projections extending in a direction from the thirdregion toward the fourth region, the channel semiconductor portion isplaced between the projections, and the drift semiconductor portion isconnected to the buried semiconductor portion, wherein the driftsemiconductor portion has a fifth region extending in the axialdirection intersecting with the principal surface of the drainsemiconductor portion, the transistor further comprising a secondsemiconductor portion having a conductivity type opposite to aconductivity type of the drain semiconductor portion and placed abovethe fifth region, wherein the second semiconductor portion extends fromthe buried semiconductor portion in the predetermined axial directionalong a source semiconductor portion.
 4. The vertical junction fieldeffect transistor according to any one of claims 1 to 3, furthercomprising a first semiconductor portion placed on the channelsemiconductor portion and the first and second regions of the driftsemiconductor portion and having the same conductivity type as thesource semiconductor portion, wherein a dopant concentration of thefirst semiconductor portion is lower than a dopant concentration of thechannel semiconductor portion.
 5. A vertical junction field effecttransistor comprising: a drain semiconductor portion; a driftsemiconductor portion placed on a principal surface of the drainsemiconductor portion and having first to fifth regions extending in apredetermined axial direction intersecting with a reference planeextending along the principal surface; a buried semiconductor portionhaving a conductivity type opposite to a conductivity type of the driftsemiconductor portion and placed along the reference plane on the firstto fourth regions of the drift semiconductor portion; a plurality ofgate semiconductor portions placed along the reference plane on thesecond to fourth regions of the drift semiconductor portion and havingthe same conductivity type as the conductivity type of the buriedsemiconductor portion; a channel semiconductor portion placed betweenthe buried semiconductor portion and the plurality of gate semiconductorportions, and between the plurality of gate semiconductor portions, andhaving the conductivity type opposite to the conductivity type of theburied semiconductor portion; a connection semiconductor portion havingthe same conductivity type as the conductivity type of the buriedsemiconductor portion and the channel semiconductor portion, extendingin the predetermined axial direction, and connecting the buriedsemiconductor portion and the plurality of gate semiconductor portions;a first aggregate semiconductor portion connecting the channelsemiconductor portion on the first region of the drift semiconductorportion; a second aggregate semiconductor portion connecting the channelsemiconductor portion on the fifth region of the drift semiconductorportion; and a source semiconductor portion placed above the firstregion of the drift semiconductor portion and connected to the firstaggregate semiconductor portion.
 6. A vertical junction field effecttransistor comprising: a drain semiconductor portion; a driftsemiconductor portion placed on a principal surface of the drainsemiconductor portion and having first to fifth regions extending in apredetermined axial direction intersecting with a reference planeextending along the principal surface; a buried semiconductor portionhaving a conductivity type opposite to a conductivity type of the driftsemiconductor portion and placed along the reference plane on the firstto fourth regions of the drift semiconductor portion; a plurality ofgate semiconductor portions placed along the reference plane on thesecond to fourth regions of the drift semiconductor portion and havingthe same conductivity type as the conductivity type of the buriedsemiconductor portion; a channel semiconductor portion placed betweenthe buried semiconductor portion and the plurality of gate semiconductorportions, and between the plurality of gate semiconductor portions, andhaving the conductivity type opposite to the conductivity type of theburied semiconductor portion; a connection semiconductor portion havingthe same conductivity type as the conductivity type of the channelsemiconductor portion and connecting the plurality of gate semiconductorportions; a first aggregate semiconductor portion connecting the channelsemiconductor portion on the first region of the drift semiconductorportion; a second aggregate semiconductor portion connecting the channelsemiconductor portion on the fifth region of the drift semiconductorportion; and a source semiconductor portion placed above the firstregion of the drift semiconductor portion and connected to the firstaggregate semiconductor portion; wherein the drift semiconductor portionhas a sixth region provided on a principal surface thereof and extendingin the direction intersecting with the principal surface, the transistorfurther comprising a third connection semiconductor portion having aconductivity type opposite to a conductivity type of the drainsemiconductor portion and placed above the sixth region, wherein thethird connection semiconductor portion is placed along the firstaggregate semiconductor portion.
 7. The vertical junction field effecttransistor according to any one of claims 1 to 4, wherein a thickness ofthe gate semiconductor portion and the channel semiconductor portion issmaller than a space between the source semiconductor portion and theburied semiconductor portion on the first region of the driftsemiconductor portion.
 8. The vertical junction field effect transistoraccording to claim 5 or 6, wherein a thickness of the gate semiconductorportions and the channel semiconductor portion on the second to fourthregions of the drift semiconductor portion is smaller than a spacebetween the source semiconductor portion and the buried semiconductorportion on the first region of the drift semiconductor portion.
 9. Thevertical junction field effect transistor according to any one of claims1, 2, and 4, wherein a space between the projections of the gatesemiconductor portion is determined so that the vertical junction fieldeffect transistor can exhibit the normally-off characteristic.
 10. Thevertical junction field effect transistor according to claim 3, whereina space between the projections of the gate semiconductor portion and aspace between the projections of the gate semiconductor portion and theburied semiconductor portion are determined so that the verticaljunction field effect transistor can exhibit the normally-offcharacteristic.
 11. The vertical junction field effect transistoraccording to any one of claims 5 to 7, wherein a space between the gatesemiconductor portions, and a space between the gate semiconductorportions and the buried semiconductor portion are determined so that thevertical junction field effect transistor can exhibit the normally-offcharacteristic.
 12. The vertical junction field effect transistoraccording to any one of claims 1 to 11, wherein the channelsemiconductor portion has a structure in which low-concentration layersand high-concentration layers are alternately stacked.
 13. The verticaljunction field effect transistor according to any one of claims 1 to 11,wherein the drift semiconductor portion has: an electroconductivesemiconductor region extending along a reference plane intersecting withthe principal surface of the drain semiconductor portion, having thesame conductivity type as the conductivity type of the drainsemiconductor portion, and electrically connected to the channelsemiconductor portion; and a non-electroconductive semiconductor regionplaced next to the electroconductive semiconductor region, having theconductivity type opposite to the conductivity type of the drainsemiconductor portion, and electrically connected to the buriedsemiconductor portion; and wherein the electroconductive semiconductorregion and the non-electroconductive semiconductor region are formed inthe same direction as a direction in which the first to fourth regionsof the drift semiconductor portion are arranged.
 14. The verticaljunction field effect transistor according to any one of claims 1 to 11,wherein the drift semiconductor portion has: an electroconductivesemiconductor region extending along a reference plane intersecting withthe principal surface of the drain semiconductor portion, having thesame conductivity type as the conductivity type of the drainsemiconductor portion, and electrically connected to the channelsemiconductor portion; and a non-electroconductive semiconductor regionplaced next to the electroconductive semiconductor region, having theconductivity type opposite to the conductivity type of the drainsemiconductor portion, and electrically connected to the buriedsemiconductor portion; and wherein the electroconductive semiconductorregion and the non-electroconductive semiconductor region are formed ina direction intersecting with a direction in which the first to fourthregions of the drift semiconductor portion are arranged.
 15. Thevertical junction field effect transistor according to any one of claims1 to 14, wherein the drain semiconductor portion, the driftsemiconductor portion, the buried semiconductor portion, the gatesemiconductor portion, the channel semiconductor portion, the connectionsemiconductor portion, and the source semiconductor portion are made ofSiC or GaN which is a wide-gap semiconductor material.
 16. A method ofproducing a vertical junction field effect transistor, comprising: astep of forming a first semiconductor layer of a first conductivity typeon a substrate of the first conductivity type, wherein a principalsurface of the first semiconductor layer has first to fourth regionsarranged in order in a predetermined axial direction; a step ofintroducing a dopant of a second conductivity type into the first tothird regions of the principal surface of the first semiconductor layerto form a buried semiconductor portion; a step of forming a secondsemiconductor layer of the first conductivity type on the firstsemiconductor layer; a step of forming a source semiconductor layer ofthe first conductivity type on the second semiconductor layer; a step ofetching the source semiconductor layer above at least one of the second,third, and fourth regions of the principal surface of the firstsemiconductor layer, up to the first semiconductor layer to expose apredetermined region of the second semiconductor layer, wherein thepredetermined region has a plurality of first portions extending in thepredetermined axial direction, and a second portion defined so as toembrace the plurality of portions; and a step of introducing a dopant ofthe second conductivity type for a gate semiconductor portion into theplurality of first portions to form a first semiconductor portion of thesecond conductivity type.
 17. The method according to claim 16, furthercomprising a step of introducing a dopant of the second conductivitytype for the gate semiconductor portion into the second portion to forma second semiconductor portion of the second conductivity type, whereina depth of the second semiconductor portion is smaller than a depth ofthe first semiconductor portion.
 18. The method according to claim 16 or17, wherein the first semiconductor portion is formed so as to beconnected to the buried semiconductor portion.
 19. A method of producinga vertical junction field effect transistor, comprising: a firstsemiconductor layer forming step of forming a first semiconductor layerof a first conductivity type on a substrate of the first conductivitytype, wherein a principal surface of the first semiconductor layer hasfirst to fourth regions arranged in order in a predetermined axialdirection; a buried semiconductor portion forming step of introducing adopant of a second conductivity type into the first to third regions ofthe principal surface of the first semiconductor layer to form a buriedsemiconductor portion; a second semiconductor layer forming step offorming a second semiconductor layer of the first conductivity type onthe first semiconductor layer; a second semiconductor region step ofintroducing a dopant of the second conductivity type for a gatesemiconductor portion into the second semiconductor layer on the secondand third regions of the principal surface of the first semiconductorlayer up to a predetermined depth to form a second semiconductor regionof the second conductivity type; a channel semiconductor portion formingstep of repeating the second semiconductor layer forming step and thesecond semiconductor region step before obtaining a desired number ofsaid second semiconductor layers, to form a stack of gate semiconductorportions and channel semiconductor portions; and a source semiconductorportion forming step of forming a source semiconductor portion on thechannel semiconductor portion.
 20. The method according to claim 19,wherein the second semiconductor layer forming step comprises formingthe second semiconductor layer of the first conductivity type in apredetermined thickness on the first semiconductor layer, and whereinthe channel semiconductor portion forming step comprises introducing thedopant of the second conductivity type so as to achieve a maximumconcentration in a predetermined depth in the second semiconductorlayer, thereby forming the stack of gate semiconductor portions andchannel semiconductor portions.
 21. The method according to claim 20,wherein the channel semiconductor portion forming step comprisesalternately introducing a first dopant and a second dopant so as toachieve a maximum concentration in a predetermined depth in the secondsemiconductor layer, thereby forming the stack of gate semiconductorportions and channel semiconductor portions.
 22. The method according toany one of claims 19 to 21, wherein the channel semiconductor portionforming step comprises a connection region forming step of forming asecond semiconductor connection region of the second conductivity typeso as to connect interiors of the second semiconductor layers to eachother.
 23. The method according to any one of claims 16 to 22, whereinthe step of forming the first semiconductor layer comprises forming thefirst semiconductor layer so as to form an electroconductivesemiconductor layer of the same conductivity type as the substrate ofthe first conductivity type, form a non-electroconductive semiconductorlayer of the conductivity type opposite to that of the electroconductivesemiconductor layer, on the electroconductive semiconductor layer, andelectrically connect the electroconductive semiconductor layer to thechannel semiconductor portion.
 24. The method according to any one ofclaims 16 to 22, wherein the step of forming the first semiconductorlayer comprises forming the first semiconductor layer so as to form anon-electroconductive semiconductor layer of the conductivity typeopposite to the substrate of the first conductivity type, form anelectroconductive semiconductor layer of the conductivity type oppositeto that of the non-electroconductive semiconductor layer, on thenon-electroconductive semiconductor layer, and electrically connect theelectroconductive semiconductor layer to the channel semiconductorportion.
 25. The method according to any one of claims 16 to 22, whereinthe step of forming the first semiconductor layer comprises forming theelectroconductive semiconductor layer and the non-electroconductivesemiconductor layer in a direction intersecting with the principalsurface of the substrate, thereby forming the first semiconductor layer.26. The vertical junction field effect transistor according to claim 3,further comprising a source electrode electrically connected to thesource semiconductor portion and the second semiconductor portion,wherein the buried semiconductor portion is electrically connectedthrough the second semiconductor portion to the source electrode.
 27. Avertical junction field effect transistor comprising: a drainsemiconductor portion; a drift semiconductor portion placed on aprincipal surface of the drain semiconductor portion and having first,second, third, and fourth regions extending in a direction intersectingwith the principal surface; a buried semiconductor portion having aconductivity type opposite to a conductivity type of the driftsemiconductor portion and placed on the first, second, and fourthregions of the drift semiconductor portion; a channel semiconductorportion placed along the buried semiconductor portion on the first andsecond regions, having a conductivity type different from theconductivity type of the buried semiconductor portion, and electricallyconnected to the third region of the drift semiconductor portion; asource semiconductor portion placed on the channel semiconductor portionand the first region of the drift semiconductor portion; a first gatesemiconductor portion having the same conductivity type as the buriedsemiconductor portion, electrically connected to the buriedsemiconductor portion, and placed above the fourth region of the driftsemiconductor portion; a first gate electrode electrically connected tothe first gate semiconductor portion above the fourth region of thedrift semiconductor portion; and a source electrode electricallyconnected to the source semiconductor portion above the first region ofthe drift semiconductor portion, electrically isolated from the firstgate electrode above the first gate electrode, and placed above thefirst, second, third, and fourth regions of the drift semiconductorportion.
 28. The vertical junction field effect transistor according toclaim 27, further comprising a second gate semiconductor portion havinga conductivity type opposite to a conductivity type of the drainsemiconductor portion and placed above the second region or above thesecond and third regions of the drift semiconductor portion, wherein thechannel semiconductor portion is placed between the buried semiconductorportion and the second gate semiconductor portion, and wherein a secondgate electrode electrically connected to the second gate semiconductorportion and electrically isolated under the source electrode is placedabove the second region or above the second and third regions of thedrift semiconductor portion.
 29. A vertical junction field effecttransistor comprising: a drain semiconductor portion; a driftsemiconductor portion placed on a principal surface of the drainsemiconductor portion and having first, second, third, and fourthregions extending in a direction intersecting with the principalsurface; a buried semiconductor portion having a conductivity typeopposite to a conductivity type of the drift semiconductor portion andplaced on the first, second, and fourth regions of the driftsemiconductor portion; a channel semiconductor portion placed along theburied semiconductor portion on the first and second regions, having aconductivity type different from the conductivity type of the buriedsemiconductor portion, and electrically connected to the third region ofthe drift semiconductor portion; a source semiconductor portion placedon the channel semiconductor portion and the first region of the driftsemiconductor portion; a first gate semiconductor portion having thesame conductivity type as the buried semiconductor portion, electricallyconnected to the buried semiconductor portion, and placed above thefourth region of the drift semiconductor portion; a source electrodeelectrically connected to the source semiconductor portion above thefirst region of the drift semiconductor portion, electrically isolatedfrom the first gate electrode above the first gate electrode, and placedabove the first, second, third, and fourth regions of the driftsemiconductor portion; and a second gate semiconductor portion having aconductivity type opposite to a conductivity type of the drainsemiconductor portion and placed above the second region or above thesecond and third regions of the drift semiconductor portion; wherein thechannel semiconductor portion is placed between the buried semiconductorportion and the second gate semiconductor portion, wherein a second gateelectrode electrically connected to the second gate semiconductorportion and electrically isolated under the source electrode is placedabove the second region or above the second and third regions of thedrift semiconductor portion, and wherein the first gate semiconductorportion and the source semiconductor portion are electrically connectedby the source electrode.
 30. A vertical junction field effect transistorcomprising: a drain semiconductor portion; a drift semiconductor portionplaced on a principal surface of the drain semiconductor portion andhaving first, second, and third regions extending in a directionintersecting with the principal surface; a buried semiconductor portionhaving a conductivity type opposite to a conductivity type of the driftsemiconductor portion and placed on the first, second, and third regionsof the drift semiconductor portion; a channel semiconductor portionplaced along the buried semiconductor portion on the first and secondregions, having a conductivity type different from the conductivity typeof the buried semiconductor portion, and electrically connected to thethird region of the drift semiconductor portion; a source semiconductorportion placed on the channel semiconductor portion and the first regionof the drift semiconductor portion; a second gate semiconductor portionhaving a conductivity type opposite to a conductivity type of the drainsemiconductor portion and placed above the second region or above thesecond and third regions of the drift semiconductor portion; a secondgate electrode placed above the second region or above the second andthird regions of the drift semiconductor portion, electrically connectedto the second gate semiconductor portion, and electrically isolatedunder the source electrode; a source electrode electrically connected tothe source semiconductor portion above the first region of the driftsemiconductor portion, electrically isolated from the second gateelectrode above the second gate electrode, and placed above the first,second, and third regions of the drift semiconductor portion; andconnection semiconductor portions having the same conductivity type asthe buried semiconductor portion, penetrating the channel semiconductorportion so as to electrically connect the second gate semiconductorportion and the buried semiconductor portion, and scattered above thesecond region of the drift semiconductor portion.
 31. The verticaljunction field effect transistor according to any one of claims 27 to30, further comprising a first semiconductor portion placed on thechannel semiconductor portion and the first region of the driftsemiconductor portion and having the same conductivity type as aconductivity type of the source semiconductor portion, wherein animpurity concentration of the first semiconductor portion is lower thanan impurity concentration of the channel semiconductor portion.
 32. Thevertical junction field effect transistor according to any one of claims27 to 31, wherein at least one of the first and second gate electrodesis provided as a gate electrode in a peripheral portion of a primitivecell or chip comprised of a plurality of transistors.
 33. The verticaljunction field effect transistor according to claim 6, wherein the firstgate semiconductor portion and the source semiconductor portion areelectrically connected by the source electrode, to a peripheral portionof a primitive cell or chip comprised of a plurality of transistors. 34.The vertical junction field effect transistor according to any one ofclaims 28 to 33, wherein the second gate semiconductor portion and thechannel semiconductor portion are provided so as to constitute aheterojunction.
 35. The vertical junction field effect transistoraccording to any one of claims 27 to 34, wherein a thickness of thechannel semiconductor portion placed above the second region of thedrift semiconductor portion is smaller than a space between the sourcesemiconductor portion and the buried semiconductor portion placed on thefirst region of the drift semiconductor portion.
 36. The verticaljunction field effect transistor according to any one of claims 27 to35, wherein a thickness of the channel semiconductor portion placedabove the second region of the drift semiconductor portion is determinedso that the vertical junction field effect transistor can exhibit thenormally-off characteristic.
 37. The vertical junction field effecttransistor according to any one of claims 27 to 36, wherein the channelsemiconductor portion has a structure in which low-concentration layersand high-concentration layers are alternately stacked.
 38. The verticaljunction field effect transistor according to any one of claims 27 to37, wherein the drift semiconductor portion has an electroconductivesemiconductor region extending along a reference plane intersecting withthe principal surface of the drain semiconductor portion, having thesame conductivity type as the drain semiconductor portion, andelectrically connected from the third region of the drift semiconductorportion to the channel semiconductor portion; and anon-electroconductive semiconductor region placed next to theelectroconductive semiconductor region, having the conductivity typeopposite to the conductivity type of the drain semiconductor portion,and electrically connected to the buried semiconductor portion; andwherein the electroconductive semiconductor region and thenon-electroconductive semiconductor region are formed in the samedirection as a direction in which the first to fourth regions of thedrift semiconductor portion are arranged.
 39. The vertical junctionfield effect transistor according to any one of claims 27 to 37, whereinthe drift semiconductor portion has an electroconductive semiconductorregion extending along a reference plane intersecting with the principalsurface of the drain semiconductor portion, having the same conductivitytype as the drain semiconductor portion, and electrically connected fromthe third region of the drift semiconductor portion to the channelsemiconductor portion; and a non-electroconductive semiconductor regionplaced next to the electroconductive semiconductor region, having theconductivity type opposite to the conductivity type of the drainsemiconductor portion, and electrically connected to the buriedsemiconductor portion; and wherein the electroconductive semiconductorregion and the non-electroconductive semiconductor region are formed ina direction intersecting with a direction in which the first to fourthregions of the drift semiconductor portion are arranged.
 40. Thevertical junction field effect transistor according to any one of claims27 to 39, wherein the drain semiconductor portion, the driftsemiconductor portion, the first gate semiconductor portion, and thechannel semiconductor portion are made of SiC or GaN which is a wide-gapsemiconductor material.
 41. A method of producing a vertical junctionfield effect transistor, comprising: a step of forming a driftsemiconductor layer having first, second, third, and fourth regions, ona substrate of a first conductivity type; a step of introducing animpurity of a conductivity type opposite to a conductivity type of thedrift semiconductor layer, into the first, second, and fourth regions ofthe drift semiconductor layer to form a buried semiconductor portion; astep of forming a channel semiconductor portion having a conductivitytype different from the conductivity type of the buried semiconductorportion, on the buried semiconductor portion and the drift semiconductorlayer; a step of forming a source semiconductor portion above the firstregion of the drift semiconductor layer; a step of introducing animpurity of the same conductivity type as the conductivity type of theburied semiconductor portion, into a portion above the fourth region ofthe drift semiconductor layer to form a first gate semiconductorportion; a step of forming a first gate electrode electrically connectedto the first gate semiconductor portion; a step of forming an interlayerfilm electrically isolated from the first gate electrode; and a step offorming a source electrode electrically connected to the sourcesemiconductor portion, on the interlayer film.
 42. The method accordingto claim 41, further comprising: a step of introducing an impurity ofthe same conductivity type as the conductivity type of the first gatesemiconductor portion, into the second region or into the second andthird regions of the drift semiconductor layer, prior to the step offorming the first gate semiconductor portion, to form a second gatesemiconductor portion, wherein a second gate electrode electricallyconnected to the second gate semiconductor portion is formed in the stepof forming the first gate electrode.
 43. A method of producing avertical junction field effect transistor, comprising: a step of forminga drift semiconductor layer having first, second, third, and fourthregions, on a substrate of a first conductivity type; a step ofintroducing an impurity of a conductivity type opposite to aconductivity type of the drift semiconductor layer, into the first,second, and fourth regions of the drift semiconductor layer to form aburied semiconductor portion; a step of forming a channel semiconductorportion having a conductivity type different from the conductivity typeof the buried semiconductor portion, on the buried semiconductor portionand the drift semiconductor layer; a step of forming a sourcesemiconductor portion above the first region of the drift semiconductorlayer; a step of introducing an impurity of the same conductivity typeas the conductivity type of the buried semiconductor portion, into thesecond region or into the second and third regions of the driftsemiconductor layer to form a second gate semiconductor portion; a stepof introducing an impurity of the same conductivity type as theconductivity type of the buried semiconductor portion, into a portionabove the fourth region of the drift semiconductor layer to form a firstgate semiconductor portion; a step of forming a second gate electrodeelectrically connected to the second gate semiconductor portion; and astep of forming a source electrode electrically connecting the sourcesemiconductor portion and, a first semiconductor portion placed on thechannel semiconductor portion and the first region of the driftsemiconductor layer and having the same conductivity type as the sourcesemiconductor portion.
 44. A method of producing a vertical junctionfield effect transistor, comprising: a step of forming a driftsemiconductor layer having first, second, third, and fourth regions, ona substrate of a first conductivity type; a step of introducing animpurity of a conductivity type opposite to a conductivity type of thedrift semiconductor layer, into the first, second, and fourth regions ofthe drift semiconductor layer to form a buried semiconductor portion; astep of forming a channel semiconductor portion having a conductivitytype different from the conductivity type of the buried semiconductorportion, on the buried semiconductor portion and the drift semiconductorlayer; a step of forming a source semiconductor portion above the firstregion of the drift semiconductor layer; a step of introducing animpurity having the same conductivity type as the conductivity type ofthe buried semiconductor portion, into the second region or into thesecond and third regions of the drift semiconductor layer to form asecond gate semiconductor portion; a step of introducing an impurity ofthe same conductivity type as the conductivity type of the buriedsemiconductor portion, into portions above the second region of thedrift semiconductor layer to form connection semiconductor portionsconnecting the second gate semiconductor portion and the buriedsemiconductor portion, in a scattered state; and a step of forming asecond gate electrode electrically connected to the second gatesemiconductor portion.
 45. The method according to any one of claims 41to 44, further comprising: a step of forming a first semiconductorportion having the same conductivity type as the source semiconductorportion, on the channel semiconductor portion, prior to the step offorming the source semiconductor portion, wherein an impurityconcentration of the first semiconductor portion is lower than animpurity concentration of the channel semiconductor portion.
 46. Themethod according to any one of claims 41, 43, and 44, wherein the stepof forming the drift semiconductor layer comprises forming the driftsemiconductor layer so as to form an electroconductive semiconductorlayer of the same conductivity type as the drain semiconductor portion,form a non-electroconductive semiconductor layer of the conductivitytype opposite to that of the electroconductive semiconductor layer, inthe electroconductive semiconductor layer, and electrically connect theelectroconductive semiconductor layer to the channel semiconductorportion.
 47. The method according to any one of claims 41, 43, and 44,wherein the step of forming the drift semiconductor layer comprisesforming the drift semiconductor layer so as to form anon-electroconductive semiconductor layer of the conductivity typeopposite to that of the drift semiconductor portion, form anelectroconductive semiconductor layer of the conductivity type oppositeto that of the non-electroconductive semiconductor layer, in thenon-electroconductive semiconductor layer, and electrically connect theelectroconductive semiconductor layer to the channel semiconductorportion.